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Features
* * * *
80C51 Core Architecture 256 Bytes of On-chip RAM 2048 Bytes of On-chip ERAM 64K Bytes of On-chip Flash Memory - Data Retention: 10 Years at 85C - Read/Write Cycle: 100K * 2K Bytes of On-chip Flash for Bootloader * 2K Bytes of On-chip EEPROM Read/Write Cycle: 100K * Integrated Power Monitor (POR: PFD) To Supervise Internal Power Supply * 14-sources 4-level Interrupts * Three 16-bit Timers/Counters * Full Duplex UART Compatible 80C51 * High-speed Architecture - In Standard Mode: 40 MHz (Vcc 3V to 5.5V, both Internal and external code execution) 60 MHz (Vcc 4.5V to 5.5V and Internal Code execution only) - In X2 mode (6 Clocks/machine cycle) 20 MHz (Vcc 3V to 5.5V, both Internal and external code execution) 30 MHz (Vcc 4.5V to 5.5V and Internal Code execution only) * Five Ports: 32 + 4 Digital I/O Lines * Five-channel 16-bit PCA with - PWM (8-bit) - High-speed Output - Timer and Edge Capture * Double Data Pointer * 21-bit WatchDog Timer (7 Programmable Bits) * A 10-bit Resolution Analog to Digital Converter (ADC) with 8 Multiplexed Inputs * SPI Interface, (PLCC52, VPFP64 and CABGA 64 packages only) * Full CAN Controller - Fully Compliant with CAN Rev 2.0A and 2.0B - Optimized Structure for Communication Management (Via SFR) - 15 Independent Message Objects - Each Message Object Programmable on Transmission or Reception - Individual Tag and Mask Filters up to 29-bit Identifier/Channel - 8-byte Cyclic Data Register (FIFO)/Message Object - 16-bit Status and Control Register/Message Object - 16-bit Time-Stamping Register/Message Object - CAN Specification 2.0 Part A or 2.0 Part B Programmable for Each Message Object - Access to Message Object Control and Data Registers Via SFR - Programmable Reception Buffer Length Up To 15 Message Objects - Priority Management of Reception of Hits on Several Message Objects at the Same Time (Basic CAN Feature) - Priority Management for Transmission - Message Object Overrun Interrupt - Supports - Time Triggered Communication - Autobaud and Listening Mode - Programmable Automatic Reply Mode - 1-Mbit/s Maximum Transfer Rate at 8 MHz (1) Crystal Frequency in X2 Mode - Readable Error Counters - Programmable Link to On-chip Timer for Time Stamping and Network Synchronization - Independent Baud Rate Prescaler - Data, Remote, Error and Overload Frame Handling 1. At BRP = 1 sampling point will be fixed.
Enhanced 8-bit MCU with CAN Controller and Flash Memory
AT89C51CC03
Rev. 4182I-CAN-06/05
* On-chip Emulation Logic (Enhanced Hook System) * Power Saving Modes
- Idle Mode - Power-down Mode * Power Supply: 3 volts to 5.5 volts * Temperature Range: Industrial (-40 to +85C), Automotive (-40C to +125C) * Packages: VQFP44, PLCC44, VQFP64, PLCC52, CA-BGA64
Description
The AT89C51CC03 is a member of the family of 8-bit microcontrollers dedicated to CAN network applications. In X2 mode a maximum external clock rate of 20 MHz reaches a 300 ns cycle time. Besides the full CAN controller AT89C51CC03 provides 64K Bytes of Flash memory including In-System Programming (ISP), 2K Bytes Boot Flash Memory, 2K Bytes EEPROM and 2048 byte ERAM. Primary attention is paid to the reduction of the electro-magnetic emission of AT89C51CC03.
Block Diagram
RxDC CAN CONTROLLER T2EX RxD TxD Vcc Vss PCA ECI T2 TxDC
XTAL1 XTAL2 ALE PSEN CPU UART RAM 256x8
C51 CORE
Flash Boot EE 64k x 8 loader PROM 2kx8 2kx8 IB-bus
ERAM 2048
PCA
Timer2
EA RD WR Timer 0 Timer 1 INT Ctrl Parallel I/O Ports and Ext. Bus Watch Dog Port 0 Port 1 Port 2 Port 3 Port 4 Emul Unit 10 bit ADC SPI Interface
P1(1)
P4(2)
RESET
Notes:
1. 8 analog Inputs/8 Digital I/O 2. 5-Bit I/O Port
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MOSI SCK MISO
P2
T0
T1
INT0
INT1
P0
P3
AT89C51CC03
Pin Configuration
P1.3/AN3/CEX0 P1.2/AN2/ECI P1.1/AN1/T2EX P1.0/AN 0/T2 VAREF VAGND RESET VSS VCC XTAL1 XTAL2 P1.4/AN4/CEX1 P1.5/AN5/CEX2 P1.6/AN6/CEX3 P1.7/AN7/CEX4 EA P3.0/RxD P3.1/TxD P3.2/INT0 P3.3/INT1 P3.4/T0 P3.5/T1 7 8 9 10 11 12 13 14 15 16 17 6 5 4 3 2 1 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29
PLCC44
ALE PSEN P0.7/AD7 P0.6/AD6 P0.5/AD5 P0.4/AD4 P0.3/AD3 P0.2/AD2 P0.1/AD1 P0.0/AD0 P2.0/A8
P1.4/AN4/CEX1 P1.5/AN5/CEX2 P1.6/AN6/CEX3 P1.7/AN7/CEX4 EA P3.0/RxD P3.1/TxD P3.2/INT0 P3.3/INT1 P3.4/T0 P3.5/T1
P1.3/AN3/CEX0 P1.2/AN2/ECI P1.1/AN1/T2EX P1.0/AN 0/T2 VAREF VAGND RESET VSS VCC XTAL1 XTAL2
44 43 42 41 40 39 38 37 36 35 34 1 2 3 4 5 6 7 8 9 10 11 33 32 31 30 29 28 27 26 25 24 23
P3.6/WR P3.7/RD P4.0/ TxDC P4.1/RxDC P2.7/A15 P2.6/A14 P2.5/A13 P2.4/A12 P2.3/A11 P2.2/A10 P2.1/A9
18 19 20 21 22 23 24 25 26 27 28
VQFP44
ALE PSEN P0.7/AD7 P0.6/AD6 P0.5/AD5 P0.4 /AD4 P0.3 /AD3 P0.2 /AD2 P0.1 /AD1 P0.0 /AD0 P2.0/A8
12 13 14 15 16 17 18 19 20 21 22 P3.6/WR P3.7/RD P4.0/TxDC P4.1/RxDC P2.7/A15 P2.6/A14 P2.5/A13 P2.4/A12 P2.3/A11 P2.2/A10 P2.1/A9
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P1.3/AN3/CEX0 P1.2/AN2/ECI P1.1/AN1/T2EX P1.0/AN 0/T2
VAGND RESET VSS TESTI VCC
2
VAREF
7
6
54
3
1 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34
P1.4/AN4/CEX1 P1.5/AN5/CEX2 P1.6/AN6/CEX3 P1.7/AN7/CEX4 EA NC P3.0/RxD P4.3/SCK P3.1/TxD P3.2/INT0 P3.3/INT1 P3.4/T0 P3.5/T1/SS
8 9 10 11 12 13 14 15 16 17 18 19 20
VCC XTAL1 XTAL2 ALE PSEN P0.7/AD7 P0.6/AD6 NC P0.5/AD5 P0.4 /AD4 P0.3 /AD3 P0.2 /AD2 P0.1 /AD1 P4.4/MOSI P0.0 /AD0 P2.0/A8
PLCC52
21 22 23 24 25 26 27 28 29 30 31 32 33 P3.6/WR P3.7/RD P4.0/TxDC P4.1/RxDC P2.7/A15 P2.6/A14 NC
TESTI must be connected to VSS P1.3/AN3/CEX0 P1.2/AN2/ECI P1.1/AN1/T2EX P1.0/AN0/T2 VAREF VAGND RESET VSS VSS VSS TESTI VCC VCC VCC XTAL1 XTAL2
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
P2.5/A13 P2.4/A12 P2.3/A11 P2.2/A10 P2.1/A9 P4.2/MISO
P1.4/AN4/CEX1 NC P1.5/AN5/CEX2 P1.6/AN6/CEX3 P1.7/AN7/CEX4 NC EA NC NC P3.0/RxD P4.3/SCK P3.1/TxD P3.2/INT0 P3.3/INT1 P3.4/T0 P3.5/T1/SS
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
VQFP64
48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33
NC ALE PSEN P0.7/AD7 P0.6/AD6 NC P0.5/AD5 NC NC P0.4/AD4 P0.3/AD3 P0.2/AD2 P0.1/AD1 P4.4/MOSI P0.0/AD0 P2.0/A8
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P3.6/WR P3.7/RD P4.0/TxDC P4.1/RxDC P2.7/A15 P2.6/A14 NC NC NC NC P2.5/A13 P2.4/A12 P2.3/A11 P2.2/A10 P2.1/A9 P4.2/MISO TESTI must be connected to VSS
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
AT89C51CC03
CA-BGA64 Top View
1 A B C D E F G H
P1.4/AN4
2
P1.2/AN2
3
P1.0/AN0
4
VAGND
5
VSS
6
VSS
7
XTAL1
8
XTAL2
P1.5/AN5
P1.3/AN3
P1.1/AN1
VAREF
VDD
VDD
NC
ALE
P1.7/AN7
P1.6/AN6
NC
NC
NC
NC
PSEN
P0.7
EA
NC
P4.3/SCK
NC
RESET
NC
P0.6
P0.5
P3.0
P3.1
NC
NC
NC
NC
P0.2
P0.4
P3.2
P3.3
NC
NC
NC
P4.4/MOSI
P0.1
P0.3
P3.4
P3.5
P4.0
P4.1
P2.4
P2.2
P4.2/MISO
P0.0
P3.6
P3.7
P2.7
P2.6
P2.5
P2.3
P2.1
P2.0
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Pin Name VSS TESTI VCC VAREF VAGND P0.0:7
Type GND I
Description Circuit ground Must be connected to VSS Supply Voltage Reference Voltage for ADC Reference Ground for ADC
I/O
Port 0: Is an 8-bit open drain bi-directional I/O port. Port 0 pins that have 1's written to them float, and in this state can be used as high-impedance inputs. Port 0 is also the multiplexed low-order address and data bus during accesses to external Program and Data Memory. In this application it uses strong internal pull-ups when emitting 1's. Port 0 also outputs the code Bytes during program validation. External pull-ups are required during program verification. Port 1: Is an 8-bit bi-directional I/O port with internal pull-ups. Port 1 pins can be used for digital input/output or as analog inputs for the Analog Digital Converter (ADC). Port 1 pins that have 1's written to them are pulled high by the internal pull-up transistors and can be used as inputs in this state. As inputs, Port 1 pins that are being pulled low externally will be the source of current (IIL, see section "Electrical Characteristic") because of the internal pull-ups. Port 1 pins are assigned to be used as analog inputs via the ADCCF register (in this case the internal pull-ups are disconnected). As a secondary digital function, port 1 contains the Timer 2 external trigger and clock input; the PCA external clock input and the PCA module I/O. P1.0/AN0/T2 Analog input channel 0, External clock input for Timer/counter2. P1.1/AN1/T2EX Analog input channel 1, Trigger input for Timer/counter2. P1.2/AN2/ECI Analog input channel 2, PCA external clock input. P1.3/AN3/CEX0 Analog input channel 3, PCA module 0 Entry of input/PWM output. P1.4/AN4/CEX1 Analog input channel 4, PCA module 1 Entry of input/PWM output. P1.5/AN5/CEX2 Analog input channel 5, PCA module 2 Entry of input/PWM output. P1.6/AN6/CEX3 Analog input channel 6, PCA module 3 Entry of input/PWM output. P1.7/AN7/CEX4 Analog input channel 7, PCA module 4 Entry ot input/PWM output. Port 1 receives the low-order address byte during EPROM programming and program verification. It can drive CMOS inputs without external pull-ups.
P1.0:7
I/O
P2.0:7
I/O
Port 2: Is an 8-bit bi-directional I/O port with internal pull-ups. Port 2 pins that have 1's written to them are pulled high by the internal pull-ups and can be used as inputs in this state. As inputs, Port 2 pins that are being pulled low externally will be a source of current (IIL, see section "Electrical Characteristic") because of the internal pull-ups. Port 2 emits the high-order address byte during accesses to the external Program Memory and during accesses to external Data Memory that uses 16-bit addresses (MOVX @DPTR). In this application, it uses strong internal pull-ups when emitting 1's. During accesses to external Data Memory that use 8 bit addresses (MOVX @Ri), Port 2 transmits the contents of the P2 special function register. It also receives high-order addresses and control signals during program validation. It can drive CMOS inputs without external pull-ups.
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Pin Name P3.0:7 Type I/O Description Port 3: Is an 8-bit bi-directional I/O port with internal pull-ups. Port 3 pins that have 1's written to them are pulled high by the internal pull-up transistors and can be used as inputs in this state. As inputs, Port 3 pins that are being pulled low externally will be a source of current (IIL, see section "Electrical Characteristic") because of the internal pull-ups. The output latch corresponding to a secondary function must be programmed to one for that function to operate (except for TxD and WR). The secondary functions are assigned to the pins of port 3 as follows: P3.0/RxD: Receiver data input (asynchronous) or data input/output (synchronous) of the serial interface P3.1/TxD: Transmitter data output (asynchronous) or clock output (synchronous) of the serial interface P3.2/INT0: External interrupt 0 input/timer 0 gate control input P3.3/INT1: External interrupt 1 input/timer 1 gate control input P3.4/T0: Timer 0 counter input P3.5/T1/SS: Timer 1 counter input SPI Slave Select P3.6/WR: External Data Memory write strobe; latches the data byte from port 0 into the external data memory P3.7/RD: External Data Memory read strobe; Enables the external data memory. It can drive CMOS inputs without external pull-ups. P4.0:4 I/O Port 4: Is an 2-bit bi-directional I/O port with internal pull-ups. Port 4 pins that have 1's written to them are pulled high by the internal pull-ups and can be used as inputs in this state. As inputs, Port 4 pins that are being pulled low externally will be a source of current (IIL, on the datasheet) because of the internal pull-up transistor. The output latch corresponding to a secondary function RxDC must be programmed to one for that function to operate. The secondary functions are assigned to the two pins of port 4 as follows: P4.0/TxDC: Transmitter output of CAN controller P4.1/RxDC: Receiver input of CAN controller. P4.2/MISO: Master Input Slave Output of SPI controller P4.3/SCK: Serial Clock of SPI controller P4.4/MOSI: Master Ouput Slave Input of SPI controller It can drive CMOS inputs without external pull-ups.
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Pin Name RESET
Type I/O
Description Reset: A high level on this pin during two machine cycles while the oscillator is running resets the device. An internal pull-down resistor to VSS permits power-on reset using only an external capacitor to VCC. ALE: An Address Latch Enable output for latching the low byte of the address during accesses to the external memory. The ALE is activated every 1/6 oscillator periods (1/3 in X2 mode) except during an external data memory access. When instructions are executed from an internal Flash (EA = 1), ALE generation can be disabled by the software. PSEN: The Program Store Enable output is a control signal that enables the external program memory of the bus during external fetch operations. It is activated twice each machine cycle during fetches from the external program memory. However, when executing from of the external program memory two activations of PSEN are skipped during each access to the external Data memory. The PSEN is not activated for internal fetches. EA: When External Access is held at the high level, instructions are fetched from the internal Flash. When held at the low level, AT89C51CC03 fetches all instructions from the external program memory. XTAL1: Input of the inverting oscillator amplifier and input of the internal clock generator circuits. To drive the device from an external clock source, XTAL1 should be driven, while XTAL2 is left unconnected. To operate above a frequency of 16 MHz, a duty cycle of 50% should be maintained. XTAL2: Output from the inverting oscillator amplifier.
ALE
O
PSEN
O
EA
I
XTAL1
I
XTAL2
O
I/O Configurations
Each Port SFR operates via type-D latches, as illustrated in Figure 1 for Ports 3 and 4. A CPU "write to latch" signal initiates transfer of internal bus data into the type-D latch. A CPU "read latch" signal transfers the latched Q output onto the internal bus. Similarly, a "read pin" signal transfers the logical level of the Port pin. Some Port data instructions activate the "read latch" signal while others activate the "read pin" signal. Latch instructions are referred to as Read-Modify-Write instructions. Each I/O line may be independently programmed as input or output.
Port 1, Port 3 and Port 4
Figure 1 shows the structure of Ports 1 and 3, which have internal pull-ups. An external source can pull the pin low. Each Port pin can be configured either for general-purpose I/O or for its alternate input output function. To use a pin for general-purpose output, set or clear the corresponding bit in the Px register (x = 1,3 or 4). To use a pin for general-purpose input, set the bit in the Px register. This turns off the output FET drive. To configure a pin for its alternate function, set the bit in the Px register. When the latch is set, the "alternate output function" signal controls the output level (see Figure 1). The operation of Ports 1, 3 and 4 is discussed further in the "quasi-Bidirectional Port Operation" section.
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AT89C51CC03
Figure 1. Port 1, Port 3 and Port 4 Structure
VCC ALTERNATE OUTPUT FUNCTION INTERNAL PULL-UP (1)
READ LATCH
INTERNAL BUS WRITE TO LATCH
D P1.X Q P3.X P4.X LATCH CL
P1.x P3.x P4.x
READ PIN
ALTERNATE INPUT FUNCTION
Note:
The internal pull-up can be disabled on P1 when analog function is selected.
Port 0 and Port 2
Ports 0 and 2 are used for general-purpose I/O or as the external address/data bus. Port 0, shown in Figure 3, differs from the other Ports in not having internal pull-ups. Figure 3 shows the structure of Port 2. An external source can pull a Port 2 pin low. To use a pin for general-purpose output, set or clear the corresponding bit in the Px register (x = 0 or 2). To use a pin for general-purpose input, set the bit in the Px register to turn off the output driver FET. Figure 2. Port 0 Structure
ADDRESS LOW/ CONTROL DATA READ LATCH
1
VDD
(2) P0.x (1)
D Q
0
INTERNAL BUS WRITE TO LATCH
P0.X LATCH
READ PIN
Notes:
1. Port 0 is precluded from use as general-purpose I/O Ports when used as address/data bus drivers. 2. Port 0 internal strong pull-ups assist the logic-one output for memory bus cycles only. Except for these bus cycles, the pull-up FET is off, Port 0 outputs are open-drain.
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Figure 3. Port 2 Structure
ADDRESS HIGH/ CONTROL VDD INTERNAL PULL-UP (2)
READ LATCH
1
P2.x (1)
D Q
0
INTERNAL BUS WRITE TO LATCH
P2.X LATCH
READ PIN
Notes:
1. Port 2 is precluded from use as general-purpose I/O Ports when as address/data bus drivers. 2. Port 2 internal strong pull-ups FET (P1 in FiGURE) assist the logic-one output for memory bus cycle.
When Port 0 and Port 2 are used for an external memory cycle, an internal control signal switches the output-driver input from the latch output to the internal address/data line.
Read-Modify-Write Instructions
Some instructions read the latch data rather than the pin data. The latch based instructions read the data, modify the data and then rewrite the latch. These are called "ReadModify-Write" instructions. Below is a complete list of these special instructions (see Table ). When the destination operand is a Port or a Port bit, these instructions read the latch rather than the pin:
Instruction ANL ORL XRL JBC CPL INC DEC DJNZ MOV Px.y, C CLR Px.y SET Px.y
Description logical AND logical OR logical EX-OR jump if bit = 1 and clear bit complement bit increment decrement decrement and jump if not zero move carry bit to bit y of Port x clear bit y of Port x set bit y of Port x
Example ANL P1, A ORL P2, A XRL P3, A JBC P1.1, LABEL CPL P3.0 INC P2 DEC P2 DJNZ P3, LABEL MOV P1.5, C CLR P2.4 SET P3.3
It is not obvious the last three instructions in this list are Read-Modify-Write instructions. These instructions read the port (all 8 bits), modify the specifically addressed bit and
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AT89C51CC03
write the new byte back to the latch. These Read-Modify-Write instructions are directed to the latch rather than the pin in order to avoid possible misinterpretation of voltage (and therefore, logic) levels at the pin. For example, a Port bit used to drive the base of an external bipolar transistor can not rise above the transistor's base-emitter junction voltage (a value lower than VIL). With a logic one written to the bit, attempts by the CPU to read the Port at the pin are misinterpreted as logic zero. A read of the latch rather than the pins returns the correct logic-one value.
Quasi-Bidirectional Port Operation
Port 1, Port 2, Port 3 and Port 4 have fixed internal pull-ups and are referred to as "quasi-bidirectional" Ports. When configured as an input, the pin impedance appears as logic one and sources current in response to an external logic zero condition. Port 0 is a "true bidirectional" pin. The pins float when configured as input. Resets write logic one to all Port latches. If logical zero is subsequently written to a Port latch, it can be returned to input conditions by a logical one written to the latch.
Note: Port latch values change near the end of Read-Modify-Write instruction cycles. Output buffers (and therefore the pin state) update early in the instruction after Read-ModifyWrite instruction cycle.
Logical zero-to-one transitions in Port 1, Port 2, Port 3 and Port 4 use an additional pullup (p1) to aid this logic transition (see Figure 4.). This increases switch speed. This extra pull-up sources 100 times normal internal circuit current during 2 oscillator clock periods. The internal pull-ups are field-effect transistors rather than linear resistors. Pullups consist of three p-channel FET (pFET) devices. A pFET is on when the gate senses logical zero and off when the gate senses logical one. pFET #1 is turned on for two oscillator periods immediately after a zero-to-one transition in the Port latch. A logical one at the Port pin turns on pFET #3 (a weak pull-up) through the inverter. This inverter and pFET pair form a latch to drive logical one. pFET #2 is a very weak pull-up switched on whenever the associated nFET is switched off. This is traditional CMOS switch convention. Current strengths are 1/10 that of pFET #3. Figure 4. Internal Pull-Up Configurations
2 Osc. PERIODS VCC p1(1) VCC p2 VCC p3 P1.x P2.x P3.x P4.x n
OUTPUT DATA
INPUT DATA READ PIN
Note:
Port 2 p1 assists the logic-one output for memory bus cycles.
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SFR Mapping
The Special Function Registers (SFRs) of the AT89C51CC03 fall into the following categories:
Mnemonic ACC B PSW SP
Add
Name
7 - - CY -
6 - - AC -
5 - - F0 -
4 - - RS1 -
3 - - RS0 -
2 - - OV -
1 - - F1 -
0 - - P -
E0h Accumulator F0h B Register D0h Program Status Word 81h Stack Pointer Data Pointer Low 82h byte LSB of DPTR Data Pointer High 83h byte MSB of DPTR
DPL
-
-
-
-
-
-
-
-
DPH
-
-
-
-
-
-
-
-
Mnemonic P0 P1 P2 P3 P4
Add
Name
7 - - - - -
6 - - - - -
5 - - - - -
4 - - - - P4.4 / MOSI
3 - - - - P4.3 / SCK
2 - - - - P4.2 / MISO
1 - - - - P4.1 / RxDC
0 - - - - P4.0 / TxDC
80h Port 0 90h Port 1 A0h Port 2 B0h Port 3 C0h Port 4 (x5)
Mnemonic TH0 TL0 TH1 TL1 TH2 TL2 TCON TMOD
Add 8Ch 8Ah 8Dh 8Bh CDh CCh 88h 89h
Name Timer/Counter 0 High byte Timer/Counter 0 Low byte Timer/Counter 1 High byte Timer/Counter 1 Low byte Timer/Counter 2 High byte Timer/Counter 2 Low byte Timer/Counter 0 and 1 control Timer/Counter 0 and 1 Modes
7 - - - - - - TF1 GATE1
6 - - - - - - TR1 C/T1#
5 - - - - - - TF0 M11
4 - - - - - - TR0 M01
3 - - - - - - IE1 GATE0
2 - - - - - - IT1 C/T0#
1 - - - - - - IE0 M10
0 - - - - - - IT0 M00
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Mnemonic T2CON T2MOD Add C8h C9h Name Timer/Counter 2 control Timer/Counter 2 Mode 7 TF2 - 6 EXF2 - 5 RCLK - 4 TCLK - 3 EXEN2 - 2 TR2 - 1 C/T2# T2OE 0 CP/RL2# DCEN
RCAP2H
Timer/Counter 2 CBh Reload/Capture High byte Timer/Counter 2 CAh Reload/Capture Low byte A6h A7h WatchDog Timer Reset WatchDog Timer Program
-
-
-
-
-
-
-
-
RCAP2L
-
-
-
-
-
-
-
-
WDTRST WDTPRG
- -
- -
- -
- -
- -
- S2
- S1
- S0
Mnemonic SCON SBUF SADEN SADDR
Add
Name
7 FE/SM0 - - -
6 SM1 - - -
5 SM2 - - -
4 REN - - -
3 TB8 - - -
2 RB8 - - -
1 TI - - -
0 RI - - -
98h Serial Control 99h Serial Data Buffer B9h Slave Address Mask A9h Slave Address
Mnemonic Add
Name CF
7 CR
6
5 - - - - CAPP0 CAPP1 CAPP2 CAPP3 CAPP4
4 CCF4 - - - CAPN0 CAPN1 CAPN2 CAPN3 CAPN4
3 CCF3 - - - MAT0 MAT1 MAT2 MAT3 MAT4
2 CCF2 CPS1 - - TOG0 TOG1 TOG2 TOG3 TOG4
1 CCF1 CPS0 - - PWM0 PWM1 PWM2 PWM3 PWM4
0 CCF0 ECF - - ECCF0 ECCF1 ECCF2 ECCF3 ECCF4
CCON CMOD CL CH CCAPM0 CCAPM1 CCAPM2 CCAPM3 CCAPM4 CCAP0H CCAP1H CCAP2H CCAP3H CCAP4H CCAP0L CCAP1L CCAP2L CCAP3L CCAP4L
D8h PCA Timer/Counter Control D9h PCA Timer/Counter Mode E9h PCA Timer/Counter Low byte F9h PCA Timer/Counter High byte DAh PCA Timer/Counter Mode 0 DBh PCA Timer/Counter Mode 1 DCh PCA Timer/Counter Mode 2 DDh PCA Timer/Counter Mode 3 DEh PCA Timer/Counter Mode 4
CIDL - -
WDTE - - ECOM0 ECOM1
-
ECOM2 ECOM3 ECOM4
FAh PCA Compare Capture Module 0 H CCAP0H7 CCAP0H6 CCAP0H5 CCAP0H4 CCAP0H3 CCAP0H2 CCAP0H1 CCAP0H0 FBh PCA Compare Capture Module 1 H CCAP1H7 CCAP1H6 CCAP1H5 CCAP1H4 CCAP1H3 CCAP1H2 CCAP1H1 CCAP1H0 FCh PCA Compare Capture Module 2 H CCAP2H7 CCAP2H6 CCAP2H5 CCAP2H4 CCAP2H3 CCAP2H2 CCAP2H1 CCAP2H0 FDh PCA Compare Capture Module 3 H CCAP3H7 CCAP3H6 CCAP3H5 CCAP3H4 CCAP3H3 CCAP3H2 CCAP3H1 CCAP3H0 FEh PCA Compare Capture Module 4 H CCAP4H7 CCAP4H6 CCAP4H5 CCAP4H4 CCAP4H3 CCAP4H2 CCAP4H1 CCAP4H0 EAh EBh ECh EDh EEh PCA Compare Capture Module 0 L CCAP0L7 CCAP0L6 CCAP0L5 CCAP0L4 CCAP0L3 CCAP0L2 CCAP0L1 CCAP0L0 PCA Compare Capture Module 1 L CCAP1L7 CCAP1L6 CCAP1L5 CCAP1L4 CCAP1L3 CCAP1L2 CCAP1L1 CCAP1L0 PCA Compare Capture Module 2 L CCAP2L7 CCAP2L6 CCAP2L5 CCAP2L4 CCAP2L3 CCAP2L2 CCAP2L1 CCAP2L0 PCA Compare Capture Module 3 L CCAP3L7 CCAP3L6 CCAP3L5 CCAP3L4 CCAP3L3 CCAP3L2 CCAP3L1 CCAP3L0 PCA Compare Capture Module 4 L CCAP4L7 CCAP4L6 CCAP4L5 CCAP4L4 CCAP4L3 CCAP4L2 CCAP4L1 CCAP4L0
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Mnemonic IEN0 IEN1 IPL0 IPH0 IPL1 IPH1
Add A8h E8h B8h B7h F8h F7h
Name Interrupt Enable Control 0 Interrupt Enable Control 1 Interrupt Priority Control Low 0 Interrupt Priority Control High 0 Interrupt Priority Control Low 1 Interrupt Priority Control High1
7 EA - - - - -
6 EC - PPC PPCH - -
5 ET2 - PT2 PT2H - -
4 ES - PS PSH - -
3 ET1 ESPI PT1 PT1H SPIL SPIH
2 EX1 ETIM PX1 PX1H POVRL POVRH
1 ET0 EADC PT0 PT0H PADCL PADCH
0 EX0 ECAN PX0 PX0H PCANL PCANH
Mnemonic ADCON ADCF ADCLK ADDH ADDL
Add
Name
7 - CH7 - ADAT9 -
6 PSIDLE CH6 - ADAT8 -
5 ADEN CH5 - ADAT7 -
4 ADEOC CH4 PRS4 ADAT6 -
3 ADSST CH3 PRS3 ADAT5 -
2 SCH2 CH2 PRS2 ADAT4 -
1 SCH1 CH1 PRS1 ADAT3 ADAT1
0 SCH0 CH0 PRS0 ADAT2 ADAT0
F3h ADC Control F6h ADC Configuration F2h ADC Clock F5h ADC Data High byte F4h ADC Data Low byte
Mnemonic
Add Name CAN General Control CAN General Status CAN General Interrupt CAN Bit Timing 1 CAN Bit Timing 2 CAN Bit Timing 3 CAN Enable Channel byte 1 CAN Enable Channel byte 2 CAN General Interrupt Enable CAN Interrupt Enable Channel byte 1
7 ABRQ - CANIT - - - - ENCH7 -
6 OVRQ OVFG - BRP5 SJW1 PHS22 ENCH14 ENCH6 -
5 TTC - OVRTIM BRP4 SJW0 PHS21 ENCH13 ENCH5 ENRX
4 SYNCTTC TBSY OVRBUF BRP3 - PHS20 ENCH12 ENCH4 ENTX
3 AUT- BAUD RBSY SERG BRP2 PRS2 PHS12 ENCH11 ENCH3 ENERCH
2 TEST ENFG CERG BRP1 PRS1 PHS11 ENCH10 ENCH2 ENBUF
1 ENA BOFF FERG BRP0 PRS0 PHS10 ENCH9 ENCH1 ENERG
0 GRES ERRP AERG - - SMP ENCH8 ENCH0 -
CANGCON ABh CANGSTA CANGIT CANBT1 CANBT2 CANBT3 CANEN1 CANEN2 CANGIE AAh 9Bh B4h B5h B6h CEh CFh C1h
CANIE1
C2h
-
IECH14
IECH13
IECH12
IECH11
IECH10
IECH9
IECH8
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Mnemonic CANIE2 Add Name C3h CAN Interrupt Enable Channel byte 2 CAN Status Interrupt Channel byte1 CAN Status Interrupt Channel byte2 CAN Timer Control 7 IECH7 6 IECH6 5 IECH5 4 IECH4 3 IECH3 2 IECH2 1 IECH1 0 IECH0
CANSIT1
BAh
-
SIT14
SIT13
SIT12
SIT11
SIT10
SIT9
SIT8
CANSIT2
BBh
SIT7
SIT6
SIT5
SIT4
SIT3
SIT2
SIT1
SIT0
CANTCON A1h CANTIMH CANTIML CANSTMP H CANSTMP L CANTTCH
TPRESC 7 CANTIM 15 CANTIM 7 TIMSTMP 15 TIMSTMP7
TPRESC 6 CANTIM 14 CANTIM 6 TIMSTMP 14 TIMSTMP 6 TIMTTC 14 TIMTTC 6 TEC6 REC6 CHNB2 TXOK CONCH0 MSG6 IDT9 IDT27 IDT1 IDT19 - IDT11
TPRESC 5 CANTIM 13 CANTIM 5 TIMSTMP 13 TIMSTMP 5 TIMTTC 13 TIMTTC 5 TEC5 REC5 CHNB1 RXOK RPLV MSG5 IDT8 IDT26 IDT0 IDT18 - IDT10
TPRESC 4 CANTIM 12 CANTIM 4 TIMSTMP 12 TIMSTMP 4 TIMTTC 12 TIMTTC 4 TEC4 REC4 CHNB0 BERR IDE MSG4 IDT7 IDT25 - IDT17 - IDT9
TPRESC 3 CANTIM 11 CANTIM 3 TIMSTMP 11 TIMSTMP 3 TIMTTC 11 TIMTTC 3 TEC3 REC3 AINC SERR DLC3 MSG3 IDT6 IDT24 - IDT16 - IDT8
TPRESC 2 CANTIM 10 CANTIM 2 TIMSTMP 10 TIMSTMP 2 TIMTTC 10 TIMTTC 2 TEC2 REC2 INDX2 CERR DLC2 MSG2 IDT5 IDT23 - IDT15 - IDT7
TPRESC 1 CANTIM 9 CANTIM 1 TIMSTMP 9 TIMSTMP 1 TIMTTC 9 TIMTTC 1 TEC1 REC1 INDX1 FERR DLC1 MSG1 IDT4 IDT22 - IDT14 - IDT6
TPRESC 0 CANTIM 8 CANTIM 0 TIMSTMP 8 TIMSTMP 0 TIMTTC 8 TIMTTC 0 TEC0 REC0 INDX0 AERR DLC0 MSG0 IDT3 IDT21 - IDT13 - IDT5
ADh CAN Timer high ACh CAN Timer low AFh AEh CAN Timer Stamp high CAN Timer Stamp low CAN Timer TTC high CAN Timer TTC low CAN Transmit Error Counter CAN Receive Error Counter CAN Page CAN Status Channel CAN Control Channel CAN Message Data CAN Identifier Tag byte 1(Part A)
A5h
TIMTTC 15 TIMTTC 7 TEC7 REC7 CHNB3 DLCW CONCH1 MSG7 IDT10 IDT28 IDT2 IDT20 - IDT12
CANTTCL
A4h
CANTEC CANREC CANPAGE CANSTCH
9Ch 9Dh B1h B2h
CANCONC B3h H CANMSG A3h
CANIDT1
BCh CAN Identifier Tag byte 1(PartB) CAN Identifier Tag byte 2 (PartA) CAN Identifier Tag byte 2 (PartB) CAN Identifier Tag byte 3(PartA) CAN Identifier Tag byte 3(PartB)
CANIDT2
BDh
CANIDT3
BEh
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Mnemonic
Add Name CAN Identifier Tag byte 4(PartA) CAN Identifier Tag byte 4(PartB) CAN Identifier Mask byte 1(PartA) CAN Identifier Mask byte 1(PartB) CAN Identifier Mask byte 2(PartA) CAN Identifier Mask byte 2(PartB) CAN Identifier Mask byte 3(PartA) CAN Identifier Mask byte 3(PartB) CAN Identifier Mask byte 4(PartA) CAN Identifier Mask byte 4(PartB)
7 - IDT4
6 - IDT3
5 - IDT2
4 - IDT1
3 -
2
1 -
0
CANIDT4
BFh
RTRTAG IDT0 RB1TAG
RB0TAF
IDMSK10 IDMSK28
IDMSK9 IDMSK27
IDMSK8 IDMSK26
IDMSK7 IDMSK25
IDMSK6 IDMSK24
IDMSK5 IDMSK23
IDMSK4 IDMSK22
IDMSK3 IDMSK21
CANIDM1
C4h
IDMSK2 IDMSK20
IDMSK1 IDMSK19
IDMSK0 IDMSK18
- IDMSK17
- IDMSK16
- IDMSK15
- IDMSK14
- IDMSK13
CANIDM2
C5h
- IDMSK12
- IDMSK11
- IDMSK10
- IDMSK9
- IDMSK8
- IDMSK7
- IDMSK6
- IDMSK5
CANIDM3
C6h
- IDMSK4
- IDMSK3
- IDMSK2
- IDMSK1
- RTRMSK IDMSK0 - IDEMSK
CANIDM4
C7h
Mnemonic SPCON SPSCR SPDAT Mnemonic PCON AUXR AUXR1 CKCON0 CKCON1 FCON EECON FSTA
Add
Name
7 SPR2 SPIF 7 SMOD1 DPU - CANX2 FPL3 EEPL3 -
6 SPEN 6 SMOD0 VPFDP - WDX2 FPL2 EEPL2 -
5 SSDIS OVR 5 - M0 ENBOOT PCAX2 FPL1 EEPL1 -
4 MSTR MODF 4 POF XRS2 - SIX2 FPL0 EEPL0 -
3 CPOL SPTE 3 GF1 XRS1 GF3 T2X2 FPS - -
2 CPHA UARTM 2 GF0 XRS0 0 T1X2 FMOD1 - -
1 SPR1 SPTEIE 1 PD EXTRAM - T0X2 FMOD0 EEE SEQERR
0 SPR0 MOFIE 0 IDL A0 DPS X2 SPIX2 FBUSY EEBUSY FLOAD
D4h SPI Control D5h SPI Status and Control
D6h SPI Data Add 87h 8Eh A2h 8Fh 9Fh D1h D2h D3 Name Power Control Auxiliary Register 0 Auxiliary Register 1 Clock Control 0 Clock Control 1 Flash Control EEPROM Contol Flash Status
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Table 1. SFR Mapping
0/8(2) F8h F0h E8h E0h D8h IPL1 xxxx x000 B 0000 0000 IEN1 xxxx x000 ACC 0000 0000 CCON 0000 0000 PSW 0000 0000 T2CON 0000 0000 P4 xxx1 1111 IPL0 x000 0000 P3 1111 1111 IEN0 0000 0000 P2 1111 1111 SCON 0000 0000 P1 1111 1111 TCON 0000 0000 P0 1111 1111 0/8(2) TMOD 0000 0000 SP 0000 0111 1/9 TL0 0000 0000 DPL 0000 0000 2/A TL1 0000 0000 DPH 0000 0000 3/B 4/C 5/D 6/E TH0 0000 0000 TH1 0000 0000 AUXR x001 0100 CKCON0 0000 0000 PCON 00x1 0000 7/F CMOD 00xx x000 FCON 0000 0000 T2MOD xxxx xx00 CANGIE xx00 000x SADEN 0000 0000 CANPAGE 0000 0000 SADDR 0000 0000 CANTCON 0000 0000 SBUF 0000 0000 CCAPM0 x000 0000 EECON xxxx xx00 RCAP2L 0000 0000 CANIE1 x000 0000 CANSIT1 0000 0000 CANSTCH xxxx xxxx CANGSTA x0x0 0000 AUXR1 xxxx 00x0 CCAPM1 x000 0000 FSTA xxxx xx00 RCAP2H 0000 0000 CANIE2 0000 0000 CANSIT2 0000 0000 CANCONCH xxxx xxxx CANGCON 0000 0x00 CANMSG xxxx xxxx CANGIT 0x00 0000 CCAPM2 x000 0000 SPCON 0001 0100 TL2 0000 0000 CANIDM1 xxxx xxxx CANIDT1 xxxx xxxx CANBT1 xxxx xxxx CANTIML 0000 0000 CANTTCL 0000 0000 CANTEC 0000 0000 CCAPM3 x000 0000 SPSCR 0000 0000 TH2 0000 0000 CANIDM2 xxxx xxxx CANIDT2 xxxx xxxx CANBT2 xxxx xxxx CANTIMH 0000 0000 CANTTCH 0000 0000 CANREC 0000 0000 CCAPM4 x000 0000 SPDAT xxxx xxxx CANEN1 x000 0000 CANIDM3 xxxx xxxx CANIDT3 xxxx xxxx CANBT3 xxxx xxxx CANSTMPL 0000 0000 WDTRST 1111 1111 CANEN2 0000 0000 CANIDM4 xxxx xxxx CANIDT4 xxxx xxxx IPH0 x000 0000 CANSTMPH 0000 0000 WDTPRG xxxx x000 CKCON1 xxxx xxx0 CL 0000 0000 1/9 CH 0000 0000 2/A CCAP0H 0000 0000 ADCLK xxx0 0000 CCAP0L 0000 0000 3/B CCAP1H 0000 0000 ADCON x000 0000 CCAP1L 0000 0000 4/C CCAP2H 0000 0000 ADDL 0000 0000 CCAP2L 0000 0000 5/D CCAP3H 0000 0000 ADDH 0000 0000 CCAP3L 0000 0000 6/E CCAP4H 0000 0000 ADCF 0000 0000 CCAP4L 0000 0000 IPH1 xxxx x000 7/F FFh F7h EFh E7h DFh
D0h
D7h
C8h
CFh
C0h
C7h
B8h B0h A8h A0h
BFh B7h AFh A7h
98h
9Fh
90h 88h 80h
97h 8Fh 87h
Reserved
Note: 1. Do not read or write Reserved Registers 2. These registers are bit-addressable. Sixteen addresses in the SFR space are both byte-addressable and bit-addressable. The bit-addressable SFR's are those whose address ends in 0 and 8. The bit addresses, in this area, are 0x80 through to 0xFF.
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Clock
The AT89C51CC03 core needs only 6 clock periods per machine cycle. This feature, called"X2", provides the following advantages: * * * * Divides frequency crystals by 2 (cheaper crystals) while keeping the same CPU power. Saves power consumption while keeping the same CPU power (oscillator power saving). Saves power consumption by dividing dynamic operating frequency by 2 in operating and idle modes. Increases CPU power by 2 while keeping the same crystal frequency.
In order to keep the original C51 compatibility, a divider-by-2 is inserted between the XTAL1 signal and the main clock input of the core (phase generator). This divider may be disabled by the software. An extra feature is available to start after Reset in the X2 mode. This feature can be enabled by a bit X2B in the Hardware Security Byte. This bit is described in the section "In-System Programming".
Description
The X2 bit in the CKCON register (see Table 2) allows switching from 12 clock cycles per instruction to 6 clock cycles and vice versa. At reset, the standard speed is activated (STD mode). Setting this bit activates the X2 feature (X2 mode) for the CPU Clock only (see Figure 5.). The Timers 0, 1 and 2, Uart, PCA, WatchDog or CAN switch in X2 mode only if the corresponding bit is cleared in the CKCON register. The clock for the whole circuit and peripheral is first divided by two before being used by the CPU core and peripherals. This allows any cyclic ratio to be accepted on the XTAL1 input. In X2 mode, as this divider is bypassed, the signals on XTAL1 must have a cyclic ratio between 40 to 60%. Figure 5. shows the clock generation block diagram. The X2 bit is validated on the XTAL1/2 rising edge to avoid glitches when switching from the X2 to the STD mode. Figure 6 shows the mode switching waveforms.
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Figure 5. Clock CPU Generation Diagram
X2B
Hardware byte On RESET PCON.0
IDL
X2
CKCON.0
XTAL1 XTAL2
/2
0 1
CPU Core Clock
CPU CLOCK
PD
PCON.1
CPU Core Clock Symbol and ADC /2 /2 /2 /2 /2 /2
1 0 1 0 1 0 1 0 1 0 1 0
FT0 Clock FT1 Clock FT2 Clock FUart Clock
FPca Clock FWd Clock FCan Clock
/2
1 0
/2
1 0
FSPIClock
X2
CKCON.0
PERIPH CLOCK
SPIX2
CANX2
WDX2
PCAX2
SIX2
T2X2
T1X2
T0X2
CKCON1.0 CKCON0.7 CKCON0.6 CKCON0.5 CKCON0.4 CKCON0.3 CKCON0.2 CKCON0.1
Peripheral Clock Symbol
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Figure 6. Mode Switching Waveforms
XTAL1
XTAL1/2
X2 bit
CPU clock STD Mode X2 Mode STD Mode
Note:
In order to prevent any incorrect operation while operating in the X2 mode, users must be aware that all peripherals using the clock frequency as a time reference (UART, timers...) will have their time reference divided by two. For example a free running timer generating an interrupt every 20 ms will then generate an interrupt every 10 ms. A UART with a 4800 baud rate will have a 9600 baud rate.
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Registers
Table 2. CKCON0 Register CKCON0 (S:8Fh) Clock Control Register
7 CANX2 Bit Number 7 6 WDX2 5 PCAX2 4 SIX2 3 T2X2 2 T1X2 1 T0X2 0 X2
Bit Mnemonic Description CANX2 CAN clock (1) Clear to select 6 clock periods per peripheral clock cycle. Set to select 12 clock periods per peripheral clock cycle. WatchDog clock (1) Clear to select 6 clock periods per peripheral clock cycle. Set to select 12 clock periods per peripheral clock cycle. Programmable Counter Array clock (1) Clear to select 6 clock periods per peripheral clock cycle. Set to select 12 clock periods per peripheral clock cycle. Enhanced UART clock (MODE 0 and 2) (1) Clear to select 6 clock periods per peripheral clock cycle. Set to select 12 clock periods per peripheral clock cycle. Timer2 clock (1) Clear to select 6 clock periods per peripheral clock cycle. Set to select 12 clock periods per peripheral clock cycle. Timer1 clock (1) Clear to select 6 clock periods per peripheral clock cycle. Set to select 12 clock periods per peripheral clock cycle. Timer0 clock (1) Clear to select 6 clock periods per peripheral clock cycle. Set to select 12 clock periods per peripheral clock cycle. CPU clock Clear to select 12 clock periods per machine cycle (STD mode) for CPU and all the peripherals. Set to select 6 clock periods per machine cycle (X2 mode) and to enable the individual peripherals "X2"bits.
6
WDX2
5
PCAX2
4
SIX2
3
T2X2
2
T1X2
1
T0X2
0
X2
Note:
1. This control bit is validated when the CPU clock bit X2 is set; when X2 is low, this bit has no effect.
Reset Value = 0000 0000b
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Table 3. CKCON1 Register CKCON1 (S:9Fh) Clock Control Register 1
7 6 5 4 3 2 1 0 SPIX2 Bit Number 7-1 Bit Mnemonic Description Reserved The value read from these bits is indeterminate. Do not set these bits. SPI clock (1) Clear to select 6 clock periods per peripheral clock cycle. Set to select 12 clock periods per peripheral clock cycle.
0
SPIX2
Note:
1. This control bit is validated when the CPU clock bit X2 is set; when X2 is low, this bit has no effect.
Reset Value = 0000 0000b
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Data Memory
The AT89C51CC03 provides data memory access in two different spaces: 1. The internal space mapped in three separate segments: * * * the lower 128 Bytes RAM segment. the upper 128 Bytes RAM segment. the expanded 2048 Bytes RAM segment (ERAM).
2. The external space. A fourth internal segment is available but dedicated to Special Function Registers, SFRs, (addresses 80h to FFh) accessible by direct addressing mode. Figure 8 shows the internal and external data memory spaces organization. Figure 7. Internal Memory - RAM
FFh Upper 128 Bytes Internal RAM indirect addressing Lower 128 Bytes Internal RAM direct or indirect addressing FFh Special Function Registers direct addressing
80h 7Fh
80h
00h
Figure 8. Internal and External Data Memory Organization ERAM-XRAM
FFFFh
64K Bytes External XRAM
FFh or 7FFh 256 up to 2048 Bytes Internal ERAM EXTRAM = 0 00h 0000h
EXTRAM = 1
Internal
External
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Internal Space
Lower 128 Bytes RAM The lower 128 Bytes of RAM (see Figure 8) are accessible from address 00h to 7Fh using direct or indirect addressing modes. The lowest 32 Bytes are grouped into 4 banks of 8 registers (R0 to R7). Two bits RS0 and RS1 in PSW register (see Figure 6) select which bank is in use according to Table 4. This allows more efficient use of code space, since register instructions are shorter than instructions that use direct addressing, and can be used for context switching in interrupt service routines. Table 4. Register Bank Selection
RS1 0 0 1 1 RS0 0 1 0 1 Description Register bank 0 from 00h to 07h Register bank 0 from 08h to 0Fh Register bank 0 from 10h to 17h Register bank 0 from 18h to 1Fh
The next 16 Bytes above the register banks form a block of bit-addressable memory space. The C51 instruction set includes a wide selection of single-bit instructions, and the 128 bits in this area can be directly addressed by these instructions. The bit addresses in this area are 00h to 7Fh. Figure 9. Lower 128 Bytes Internal RAM Organization
7Fh
30h 20h 18h 10h 08h 00h
2Fh 1Fh 17h 0Fh 07h
Bit-Addressable Space (Bit Addresses 0-7Fh)
4 Banks of 8 Registers R0-R7
Upper 128 Bytes RAM Expanded RAM
The upper 128 Bytes of RAM are accessible from address 80h to FFh using only indirect addressing mode. The on-chip 2048 Bytes of expanded RAM (ERAM) are accessible from address 0000h to 07FFh using indirect addressing mode through MOVX instructions. In this address range, the bit EXTRAM in AUXR register is used to select the ERAM (default) or the XRAM. As shown in Figure 8 when EXTRAM = 0, the ERAM is selected and when EXTRAM = 1, the XRAM is selected. The size of ERAM can be configured by XRS2-0 bit in AUXR register (default size is 2048 Bytes).
Note: Lower 128 Bytes RAM, Upper 128 Bytes RAM, and expanded RAM are made of volatile memory cells. This means that the RAM content is indeterminate after power-up and must then be initialized properly.
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External Space
Memory Interface The external memory interface comprises the external bus (port 0 and port 2) as well as the bus control signals (RD#, WR#, and ALE). Figure 10 shows the structure of the external address bus. P0 carries address A7:0 while P2 carries address A15:8. Data D7:0 is multiplexed with A7:0 on P0. Table 5 describes the external memory interface signals. Figure 10. External Data Memory Interface Structure
AT89C51CC03 P2 ALE P0 AD7:0 A15:8 RAM PERIPHERAL A15:8 A7:0
Latch
A7:0 D7:0
RD# WR#
OE WR
Table 5. External Data Memory Interface Signals
Signal Name A15:8 Type O Description Address Lines Upper address lines for the external bus. Address/Data Lines Multiplexed lower address lines and data for the external memory. Address Latch Enable ALE signals indicates that valid address information are available on lines AD7:0. Read Read signal output to external data memory. Write Write signal output to external memory. Alternative Function P2.7:0
AD7:0
I/O
P0.7:0
ALE
O
-
RD# WR#
O O
P3.7 P3.6
External Bus Cycles
This section describes the bus cycles the AT89C51CC03 executes to read (see Figure 11), and write data (see Figure 12) in the external data memory. External memory cycle takes 6 CPU clock periods. This is equivalent to 12 oscillator clock period in standard mode or 6 oscillator clock periods in X2 mode. For further information on X2 mode. Slow peripherals can be accessed by stretching the read and write cycles. This is done using the M0 bit in AUXR register. Setting this bit changes the width of the RD# and WR# signals from 3 to 15 CPU clock periods. For simplicity, the accompanying figures depict the bus cycle waveforms in idealized form and do not provide precise timing information. For bus cycle timing parameters refer to the Section "AC Characteristics" of the AT89C51CC03 datasheet.
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Figure 11. External Data Read Waveforms
CPU Clock ALE RD#1 P0 P2
P2 DPL or Ri D7:0
DPH or P22
Notes:
1. RD# signal may be stretched using M0 bit in AUXR register. 2. When executing MOVX @Ri instruction, P2 outputs SFR content.
Figure 12. External Data Write Waveforms
CPU Clock ALE WR#1 P0 P2 Notes:
P2 DPL or Ri D7:0
DPH or P22
1. WR# signal may be stretched using M0 bit in AUXR register. 2. When executing MOVX @Ri instruction, P2 outputs SFR content.
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Dual Data Pointer
Description The AT89C51CC03 implements a second data pointer for speeding up code execution and reducing code size in case of intensive usage of external memory accesses. DPTR 0 and DPTR 1 are seen by the CPU as DPTR and are accessed using the SFR addresses 83h and 84h that are the DPH and DPL addresses. The DPS bit in AUXR1 register (see Figure 8) is used to select whether DPTR is the data pointer 0 or the data pointer 1 (see Figure 13). Figure 13. Dual Data Pointer Implementation
DPL0 DPL1
DPTR0 DPTR1 0 1
DPL
DPS DPH0 DPH1
0 1
AUXR1.0
DPTR
DPH
Application
Software can take advantage of the additional data pointers to both increase speed and reduce code size, for example, block operations (copy, compare...) are well served by using one data pointer as a "source" pointer and the other one as a "destination" pointer. Hereafter is an example of block move implementation using the two pointers and coded in assembler. The latest C compiler takes also advantage of this feature by providing enhanced algorithm libraries. The INC instruction is a short (2 Bytes) and fast (6 machine cycle) way to manipulate the DPS bit in the AUXR1 register. However, note that the INC instruction does not directly force the DPS bit to a particular state, but simply toggles it. In simple routines, such as the block move example, only the fact that DPS is toggled in the proper sequence matters, not its actual value. In other words, the block move routine works the same whether DPS is '0' or '1' on entry.
; ASCII block move using dual data pointers ; Modifies DPTR0, DPTR1, A and PSW ; Ends when encountering NULL character ; Note: DPS exits opposite to the entry state unless an extra INC AUXR1 is added AUXR1EQU0A2h move:movDPTR,#SOURCE ; address of SOURCE incAUXR1 ; switch data pointers movDPTR,#DEST ; address of DEST mv_loop:incAUXR1; switch data pointers movxA,@DPTR; get a byte from SOURCE incDPTR; increment SOURCE address incAUXR1; switch data pointers movx@DPTR,A; write the byte to DEST incDPTR; increment DEST address jnzmv_loop; check for NULL terminator end_move:
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Registers
Table 6. PSW Register PSW (S:8Eh) Program Status Word Register
7 CY Bit Number 7 6 5 4-3 2 1 0 6 AC 5 F0 4 RS1 3 RS0 2 OV 1 F1 0 P
Bit Mnemonic Description CY AC F0 RS1:0 OV F1 P Carry Flag Carry out from bit 1 of ALU operands. Auxiliary Carry Flag Carry out from bit 1 of addition operands. User Definable Flag 0. Register Bank Select Bits Refer to Table 4 for bits description. Overflow Flag Overflow set by arithmetic operations. User Definable Flag 1 Parity Bit Set when ACC contains an odd number of 1's. Cleared when ACC contains an even number of 1's.
Reset Value = 0000 0000b Table 7. AUXR Register AUXR (S:8Eh) Auxiliary Register
7 Bit Number 7-6 6 5 M0 4 XRS2 3 XRS1 2 XRS0 1 EXTRAM 0 A0
Bit Mnemonic Description Reserved The value read from these bits are indeterminate. Do not set this bit. Stretch MOVX control: the RD/ and the WR/ pulse length is increased according to the value of M0. M0 Pulse length in clock period 0 6 1 30
5
M0
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Bit Number Bit Mnemonic Description ERAM size: Accessible size of the ERAM XRS 2:0 ERAM size 000 256 Bytes 001 512 Bytes 010 768 Bytes 011 1024 Bytes 100 101 110 111 1792 Bytes 2048 Bytes (default configuration after reset) Reserved Reserved
4-2
XRS1-0
1
EXTRAM
Internal/External RAM (00h - FFh) access using MOVX @ Ri/@ DPTR 0 - Internal ERAM access using MOVX @ Ri/@ DPTR. 1 - External data memory access. Disable/Enable ALE) 0 - ALE is emitted at a constant rate of 1/6 the oscillator frequency (or 1/3 if X2 mode is used) 1 - ALE is active only during a MOVX or MOVC instruction.
0
A0
Reset Value = X001 0100b Not bit addressable Table 8. AUXR1 Register AUXR1 (S:A2h) Auxiliary Control Register 1
7 Bit Number 7-6 6 5 ENBOOT 4 3 GF3 2 0 1 0 DPS
Bit Mnemonic Description Reserved The value read from these bits is indeterminate. Do not set these bits. Enable Boot Flash Set this bit for map the boot Flash between F800h -FFFFh Clear this bit for disable boot Flash. Reserved The value read from this bit is indeterminate. Do not set this bit. General-purpose Flag 3 Always Zero This bit is stuck to logic 0 to allow INC AUXR1 instruction without affecting GF3 flag. Reserved for Data Pointer Extension. Data Pointer Select Bit Set to select second dual data pointer: DPTR1. Clear to select first dual data pointer: DPTR0.
5
ENBOOT
4 3 2 1 0
GF3 0 DPS
Reset Value = XXXX 00X0b
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Power Monitor
The POR/PFD function monitors the internal power-supply of the CPU core memories and the peripherals, and if needed, suspends their activity when the internal power supply falls below a safety threshold. This is achieved by applying an internal reset to them. By generating the Reset the Power Monitor insures a correct start up when AT89C51CC03 is powered up.
Description
In order to startup and maintain the microcontroller in correct operating mode, VCC has to be stabilized in the VCC operating range and the oscillator has to be stabilized with a nominal amplitude compatible with logic level VIH/VIL. These parameters are controlled during the three phases: power-up, normal operation and power going down. See Figure 14.
Figure 14. Power Monitor Block Diagram
VCC
CPU core
Power On Reset Power Fail Detect Voltage Regulator
Regulated Supply
Memories
Peripherals
XTAL1
(1)
Internal Reset
RST pin
PCA Watchdog
Hardware Watchdog
Note:
1. Once XTAL1 high and low levels reach above and below VIH/VIL a 1024 clock period delay will extend the reset coming from the Power Fail Detect. If the power falls below the Power Fail Detect thresthold level, the reset will be applied immediately.
The Voltage regulator generates a regulated internal supply for the CPU core the memories and the peripherals. Spikes on the external Vcc are smoothed by the voltage regulator. The Power fail detect monitor the supply generated by the voltage regulator and generate a reset if this supply falls below a safety threshold as illustrated in the Figure 15.
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Figure 15. Power Fail Detect Vcc
t
Reset Vcc
When the power is applied, the Power Monitor immediately asserts a reset. Once the internal supply after the voltage regulator reach a safety level, the power monitor then looks at the XTAL clock input. The internal reset will remain asserted until the Xtal1 levels are above and below VIH and VIL. Further more. An internal counter will count 1024 clock periods before the reset is de-asserted. If the internal power supply falls below a safety level, a reset is immediately asserted. .
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Reset
Introduction
The reset sources are : Power Management, Hardware Watchdog, PCA Watchdog and Reset input. Figure 16. Reset Schematic
Power Monitor Hardware Watchdog PCA Watchdog Internal Reset
RST
Reset Input
The Reset input can be used to force a reset pulse longer than the internal reset controlled by the Power Monitor. RST input has a pull-down resistor allowing power-on reset by simply connecting an external capacitor to VCC as shown in Figure 17. Resistor value and input characteristics are discussed in the Section "DC Characteristics" of the AT89C51CC03 datasheet. The status of the Port pins during reset is detailed in Table 9. Figure 17. Reset Circuitry and Power-On Reset
VDD
RST
R
To internal reset
RST
+
RST b. Power-on Reset
VSS
a. RST input circuitry
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Reset Output
As detailed in Section "Watchdog Timer", page 82, the WDT generates a 96-clock period pulse on the RST pin. In order to properly propagate this pulse to the rest of the application in case of external capacitor or power-supply supervisor circuit, a 1 k resistor must be added as shown Figure 18. Figure 18. Recommended Reset Output Schematic
VDD
+
RST
VDD
1K
AT89C51CC03
RST
VSS
To other on-board circuitry
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Power Management
Introduction
Two power reduction modes are implemented in the AT89C51CC03. The Idle mode and the Power-Down mode. These modes are detailed in the following sections. In addition to these power reduction modes, the clocks of the core and peripherals can be dynamically divided by 2 using the X2 mode detailed in Section "Clock", page 18. Idle mode is a power reduction mode that reduces the power consumption. In this mode, program execution halts. Idle mode freezes the clock to the CPU at known states while the peripherals continue to be clocked. The CPU status before entering Idle mode is preserved, i.e., the program counter and program status word register retain their data for the duration of Idle mode. The contents of the SFRs and RAM are also retained. The status of the Port pins during Idle mode is detailed in Table 9. To enter Idle mode, set the IDL bit in PCON register (see Table 10). The AT89C51CC03 enters Idle mode upon execution of the instruction that sets IDL bit. The instruction that sets IDL bit is the last instruction executed.
Note: If IDL bit and PD bit are set simultaneously, the AT89C51CC03 enters Power-Down mode. Then it does not go in Idle mode when exiting Power-Down mode.
Idle Mode
Entering Idle Mode
Exiting Idle Mode
There are two ways to exit Idle mode: 1. Generate an enabled interrupt. - Hardware clears IDL bit in PCON register which restores the clock to the CPU. Execution resumes with the interrupt service routine. Upon completion of the interrupt service routine, program execution resumes with the instruction immediately following the instruction that activated Idle mode. The general purpose flags (GF1 and GF0 in PCON register) may be used to indicate whether an interrupt occurred during normal operation or during Idle mode. When Idle mode is exited by an interrupt, the interrupt service routine may examine GF1 and GF0. A logic high on the RST pin clears IDL bit in PCON register directly and asynchronously. This restores the clock to the CPU. Program execution momentarily resumes with the instruction immediately following the instruction that activated the Idle mode and may continue for a number of clock cycles before the internal reset algorithm takes control. Reset initializes the AT89C51CC03 and vectors the CPU to address C:0000h.
During the time that execution resumes, the internal RAM cannot be accessed; however, it is possible for the Port pins to be accessed. To avoid unexpected outputs at the Port pins, the instruction immediately following the instruction that activated Idle mode should not write to a Port pin or to the external RAM.
2. Generate a reset. -
Note:
Power-Down Mode
The Power-Down mode places the AT89C51CC03 in a very low power state. PowerDown mode stops the oscillator, freezes all clock at known states. The CPU status prior to entering Power-Down mode is preserved, i.e., the program counter, program status word register retain their data for the duration of Power-Down mode. In addition, the SFR and RAM contents are preserved. The status of the Port pins during Power-Down mode is detailed in Table 9.
Note: VCC may be reduced to as low as VRET during Power-Down mode to further reduce power dissipation. Take care, however, that VDD is not reduced until Power-Down mode is invoked.
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Entering Power-Down Mode To enter Power-Down mode, set PD bit in PCON register. The AT89C51CC03 enters the Power-Down mode upon execution of the instruction that sets PD bit. The instruction that sets PD bit is the last instruction executed.
Exiting Power-Down Mode
Note: If VCC was reduced during the Power-Down mode, do not exit Power-Down mode until VCC is restored to the normal operating level.
There are two ways to exit the Power-Down mode: 1. Generate an enabled external interrupt. - The AT89C51CC03 provides capability to exit from Power-Down using INT0#, INT1#. Hardware clears PD bit in PCON register which starts the oscillator and restores the clocks to the CPU and peripherals. Using INTx# input, execution resumes when the input is released (see Figure 19). Execution resumes with the interrupt service routine. Upon completion of the interrupt service routine, program execution resumes with the instruction immediately following the instruction that activated Power-Down mode.
The external interrupt used to exit Power-Down mode must be configured as level sensitive (INT0# and INT1#) and must be assigned the highest priority. In addition, the duration of the interrupt must be long enough to allow the oscillator to stabilize. The execution will only resume when the interrupt is deasserted. Exit from power-down by external interrupt does not affect the SFRs nor the internal RAM content.
Note:
Note:
Figure 19. Power-Down Exit Waveform Using INT1:0#
INT1:0# OSC Active phase Power-down phase Oscillator restart phase Active phase
2. Generate a reset. - A logic high on the RST pin clears PD bit in PCON register directly and asynchronously. This starts the oscillator and restores the clock to the CPU and peripherals. Program execution momentarily resumes with the instruction immediately following the instruction that activated Power-Down mode and may continue for a number of clock cycles before the internal reset algorithm takes control. Reset initializes the AT89C51CC03 and vectors the CPU to address 0000h.
During the time that execution resumes, the internal RAM cannot be accessed; however, it is possible for the Port pins to be accessed. To avoid unexpected outputs at the Port pins, the instruction immediately following the instruction that activated the Power-Down mode should not write to a Port pin or to the external RAM. Exit from power-down by reset redefines all the SFRs, but does not affect the internal RAM content.
Note:
Note:
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Table 9. Pin Conditions in Special Operating Modes
Mode Reset Idle (internal code) Idle (external code) PowerDown(inter nal code) PowerDown (external code) Port 0 Floating Data Port 1 High Data Port 2 High Data Port 3 High Data Port 4 High Data ALE High High PSEN# High High
Floating
Data
Data
Data
Data
High
High
Data
Data
Data
Data
Data
Low
Low
Floating
Data
Data
Data
Data
Low
Low
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Registers
Table 10. PCON Register PCON (S87:h) Power configuration Register
7 Bit Number 7-4 6 5 4 3 GF1 2 GF0 1 PD 0 IDL
Bit Mnemonic Description Reserved The value read from these bits is indeterminate. Do not set these bits. General Purpose flag 1 One use is to indicate whether an interrupt occurred during normal operation or during Idle mode. General Purpose flag 0 One use is to indicate whether an interrupt occurred during normal operation or during Idle mode. Power-Down Mode bit Cleared by hardware when an interrupt or reset occurs. Set to activate the Power-Down mode. If IDL and PD are both set, PD takes precedence. Idle Mode bit Cleared by hardware when an interrupt or reset occurs. Set to activate the Idle mode. If IDL and PD are both set, PD takes precedence.
3
GF1
2
GF0
1
PD
0
IDL
Reset Value= XXXX 0000b
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EEPROM Data Memory
The 2-Kbyte on-chip EEPROM memory block is located at addresses 0000h to 07FFh of the XRAM/ERAM memory space and is selected by setting control bits in the EECON register. A read in the EEPROM memory is done with a MOVX instruction. A physical write in the EEPROM memory is done in two steps: write data in the column latches and transfer of all data latches into an EEPROM memory row (programming). The number of data written on the page may vary from 1 up to 128 Bytes (the page size). When programming, only the data written in the column latch is programmed and a ninth bit is used to obtain this feature. This provides the capability to program the whole memory by Bytes, by page or by a number of Bytes in a page. Indeed, each ninth bit is set when the writing the corresponding byte in a row and all these ninth bits are reset after the writing of the complete EEPROM row.
Write Data in the Column Latches
Data is written by byte to the column latches as for an external RAM memory. Out of the 11 address bits of the data pointer, the 4 MSBs are used for page selection (row) and 7 are used for byte selection. Between two EEPROM programming sessions, all the addresses in the column latches must stay on the same page, meaning that the 4 MSB must no be changed. The following procedure is used to write to the column latches: * * * * * * * Save and disable interrupt. Set bit EEE of EECON register Load DPTR with the address to write Store A register with the data to be written Execute a MOVX @DPTR, A If needed loop the three last instructions until the end of a 128 Bytes page Restore interrupt.
The last page address used when loading the column latch is the one used to select the page programming address.
Note:
Programming
The EEPROM programming consists of the following actions: * writing one or more Bytes of one page in the column latches. Normally, all Bytes must belong to the same page; if not, the first page address will be latched and the others discarded. launching programming by writing the control sequence (50h followed by A0h) to the EECON register. EEBUSY flag in EECON is then set by hardware to indicate that programming is in progress and that the EEPROM segment is not available for reading. The end of programming is indicated by a hardware clear of the EEBUSY flag.
The sequence 5xh and Axh must be executed without instructions between then otherwise the programming is aborted.
* * *
Note:
Read Data
The following procedure is used to read the data stored in the EEPROM memory: * * * * * Save and disable interrupt Set bit EEE of EECON register Load DPTR with the address to read Execute a MOVX A, @DPTR Restore interrupt
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Examples
;*F*************************************************************************;* NAME: api_rd_eeprom_byte ;* DPTR contain address to read. ;* Acc contain the reading value ;* NOTE: before execute this function, be sure the EEPROM is not BUSY ;*************************************************************************** api_rd_eeprom_byte: MOV EECON, #02h; map EEPROM in XRAM space MOVX A, @DPTR MOV EECON, #00h; unmap EEPROM ret ;*F************************************************************************* ;* NAME: api_ld_eeprom_cl ;* DPTR contain address to load ;* Acc contain value to load ;* NOTE: in this example we load only 1 byte, but it is possible upto ;* 128 Bytes. ;* before execute this function, be sure the EEPROM is not BUSY ;*************************************************************************** api_ld_eeprom_cl: MOV EECON, #02h ; map EEPROM in XRAM space MOVX @DPTR, A MOVEECON, #00h; unmap EEPROM ret ;*F************************************************************************* ;* NAME: api_wr_eeprom ;* NOTE: before execute this function, be sure the EEPROM is not BUSY ;*************************************************************************** api_wr_eeprom: MOV EECON, #050h MOV EECON, #0A0h ret
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Registers
Table 11. EECON Register EECON (S:0D2h) EEPROM Control Register
7 EEPL3 6 EEPL2 Bit Mnemonic EEPL3-0 5 EEPL1 4 EEPL0 3 2 1 EEE 0 EEBUSY
Bit Number 7-4 3 2
Description Programming Launch command bits Write 5Xh followed by AXh to EEPL to launch the programming. Reserved The value read from this bit is indeterminate. Do not set this bit. Reserved The value read from this bit is indeterminate. Do not set this bit. Enable EEPROM Space bit Set to map the EEPROM space during MOVX instructions (Write in the column latches) Clear to map the XRAM space during MOVX. Programming Busy flag Set by hardware when programming is in progress. Cleared by hardware when programming is done. Can not be set or cleared by software.
1
EEE
0
EEBUSY
Reset Value = XXXX XX00b Not bit addressable
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Program/Code Memory
The AT89C51CC03 implement 64K Bytes of on-chip program/code memory. Figure 20 shows the partitioning of internal and external program/code memory spaces depending on the product. The Flash memory increases EPROM and ROM functionality by in-circuit electrical erasure and programming. Thanks to the internal charge pump, the high voltage needed for programming or erasing Flash cells is generated on-chip using the standard VDD voltage. Thus, the Flash Memory can be programmed using only one voltage and allows InSystem Programming commonly known as ISP. Hardware programming mode is also available using specific programming tool. Figure 20. Program/Code Memory Organization
FFFFh 64K Bytes internal Flash EA = 1 0000h 0000h FFFFh 64K Bytes external memory EA = 0
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External Code Memory Access
Memory Interface The external memory interface comprises the external bus (port 0 and port 2) as well as the bus control signals (PSEN#, and ALE). Figure 21 shows the structure of the external address bus. P0 carries address A7:0 while P2 carries address A15:8. Data D7:0 is multiplexed with A7:0 on P0. Table 21 describes the external memory interface signals. Figure 21. External Code Memory Interface Structure
AT89C51CC0 P2 ALE P0 AD7:0 A15:8 Flash EPROM A15:8 A7:0
Latch
A7:0 D7:0
PSEN#
OE
Table 12. External Code Memory Interface Signals
Signal Name A15:8 AD7:0 Type O I/O Description Address Lines Upper address lines for the external bus. Address/Data Lines Multiplexed lower address lines and data for the external memory. Address Latch Enable ALE signals indicates that valid address information are available on lines AD7:0. Program Store Enable Output This signal is active low during external code fetch or external code read (MOVC instruction). Alternate Function P2.7:0 P0.7:0
ALE
O
-
PSEN#
O
-
External Bus Cycles
This section describes the bus cycles the AT89C51CC03 executes to fetch code (see Figure 22) in the external program/code memory. External memory cycle takes 6 CPU clock periods. This is equivalent to 12 oscillator clock period in standard mode or 6 oscillator clock periods in X2 mode. For further information on X2 mode see section "Clock ". For simplicity, the accompanying figure depicts the bus cycle waveforms in idealized form and do not provide precise timing information. For bus cycling parameters refer to the `AC-DC parameters' section.
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Figure 22. External Code Fetch Waveforms
CPU Clock ALE PSEN# P0 D7:0 P2 PCH
PCL PCH D7:0 PCL PCH D7:0
Flash Memory Architecture
AT89C51CC03 features two on-chip Flash memories: * Flash memory FM0: containing 64K Bytes of program memory (user space) organized into 128 byte pages, Flash memory FM1: 2K Bytes for boot loader and Application Programming Interfaces (API).
*
The FM0 can be program by both parallel programming and Serial In-System Programming (ISP) whereas FM1 supports only parallel programming by programmers. The ISP mode is detailed in the "In-System Programming" section. All Read/Write access operations on Flash Memory by user application are managed by a set of API described in the "In-System Programming" section. The bit ENBOOT in AUXR1 register is used to map FM1 from F800h to FFFFh. Figure 23 and Figure 24 show the Flash memory configuration with ENBOOT=1 and ENBOOT=0. Figure 23. Flash Memory Architecture with ENBOOT=1 (boot mode)
Hardware Security (1 byte) Extra Row (128 Bytes) Column Latches (128 Bytes)
FFFFh
64K Bytes
2K Bytes Flash memory boot space FM1
FFFFh
F800h
FM0
F800h
FM1 mapped between FFFFh and F800h when bit ENBOOT is set in AUXR1 register
0000h
Memory space not accessible
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Figure 24. Flash Memory Architecture with ENBOOT=0 (user modemode)
Hardware Security (1 byte) Extra Row (128 Bytes) Column Latches (128 Bytes)
FFFFh
64K Bytes
2K Bytes Flash memory boot space FM1
FFFFh
F800h
FM0
F800h
FM1 mapped between FFFFh and F800h when bit ENBOOT is set in AUXR1 register
0000h
Memory space not accessible
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FM0 Memory Architecture The Flash memory is made up of 4 blocks (see Figure 23): * * * * User Space Extra Row (XRow) Hardware security Byte (HSB) The memory array (user space) 64K Bytes The Extra Row The Hardware security bits The column latch registers
This space is composed of a 64K Bytes Flash memory organized in 512 pages of 128 Bytes. It contains the user's application code. This row is a part of FM0 and has a size of 128 Bytes. The extra row may contain information for boot loader usage. The Hardware security Byte space is a part of FM0 and has a size of 1 byte. The 4 MSB can be read/written by software (from FM0 and , the 4 LSB can only be read by software and written by hardware in parallel mode. H Hardware Security Byte (HSB)
7 X2 Bit Number 6 BLJB Bit Mnemonic 5 4 3 2 LB2 1 LB1 0 LB0
Description X2 Mode Programmed (='0') to force X2 mode (6 clocks per instruction) after reset Unprogrammed to force X1 mode, Standard Mode, afetr reset (Default) Boot Loader Jump Bit When unprogrammed (='1'), at the next reset : -ENBOOT=0 (see code space memory configuration)
7
X2
6
BLJB
-Start address is 0000h (PC=0000h) When programmed (='0')at the nex reset: -ENBOOT=1 (see code space memory configuration) -Start address is F800h (PC=F800h)
5 4 3 2-0
LB2-0
Reserved Reserved Reserved General Memory Lock Bits (only programmable by programmer tools) Section "Flash Protection from Parallel Programming", page 54
Column Latches
The column latches, also part of FM0, have a size of full page (128 Bytes). The column latches are the entrance buffers of the three previous memory locations (user array, XROW and Hardware security byte). The column latches are write only and can be accessed only from FM1 (boot mode) and from external memory The FM0 memory can be program only from FM1. Programming FM0 from FM0 or from external memory is impossible. The FM1 memory can be program only by parallel programming. The Table show all software Flash access allowed. 45
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Cross Flash Memory Access
Action Read Code executing from FM0 (user Flash) Load column latch Write Read FM1 (boot Flash) Load column latch Write Read External memory EA = 0 Load column latch Write FM0 (user Flash) ok ok ok ok ok (a) FM1 (boot Flash) ok -
(a) Depend upon general lock bit configuration.
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Overview of FM0 Operations
Flash Registers (SFR) The CPU interfaces to the flash memory through the FCON register, AUXR1 register and FSTA register. These registers are used to map the column latches, HSB, extra row and EEDATA in the working data or code space. FCON Register Table 13. FCON Register FCON Register (S:D1h) Flash Control Register
7 FPL3 Bit Number 7-4 6 FPL2 5 FPL1 4 FPL0 3 FPS 2 FMOD1 1 FMOD0 0 FBUSY
Bit Mnemonic Description FPL3:0 Programming Launch Command Bits Write 5Xh followed by AXh to launch the programming according to FMOD1:0. (see Table 16.) Flash Map Program Space When this bit is set:
3
FPS
The MOVX @DPTR, A instruction writes in the columns latches space When this bit is cleared: The MOVX @DPTR, A instruction writes in the regular XDATA memory space
2-1
FMOD1:0
Flash Mode See Table 16. Flash Busy Set by hardware when programming is in progress. Clear by hardware when programming is done. Can not be changed by software.
0
FBUSY
Reset Value= 0000 0000b
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FSTA Register Table 14. FSTA Register FSTA Register (S:D3h) Flash Status Register
7 6 5 4 3 2 1 SEQERR Bit Number 7-2 Bit Mnemonic Description unusesd Flash activation sequence error Set by hardware when the flash activation sequence(MOV FCON 5X and MOV FCON AX )is not correct (See Error Repport Section) Clear by software or clear by hardware if the last activation sequence was correct (previous error are canceled) Flash Colums latch loaded Set by hardware when the first data is loaded in the column latches. Clear by hardware when the activation sequence suceed (flash write sucess, or reset column latch success) 0 FLOAD
1
SEQERR
0
FLOAD
Reset Value= 0000 0000b Mapping of the Memory Space By default, the user space is accessed by MOVC A, @DPTR instruction for read only. The column latches space is made accessible by setting the FPS bit in FCON register. Writing is possible from 0000h to FFFFh, address bits 6 to 0 are used to select an address within a page while bits 15 to 7 are used to select the programming address of the page. Setting FPS bit takes precedence on the EXTRAM bit in AUXR register. The other memory spaces (user, extra row, hardware security) are made accessible in the code segment by programming bits FMOD0 and FMOD1 in FCON register in accordance with Table 15. A MOVC instruction is then used for reading these spaces. Table 15. FM0 Blocks Select Bits
FMOD1 0 0 1 1 FMOD0 0 1 0 1 FM0 Adressable space User (0000h-FFFFh) Extra Row(FF80h-FFFFh) Hardware Security Byte (0000h) Column latches reset (note1)
Notes:
1. The column latches reset is a new option introduced in the AT89C51CC03, and is not available in T89C51CC01/2
Launching Programming
FPL3:0 bits in FCON register are used to secure the launch of programming. A specific sequence must be written in these bits to unlock the write protection and to launch the programming. This sequence is 5xh followed by Axh. Table 16 summarizes the memory spaces to program according to FMOD1:0 bits.
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Table 16. Programming Spaces
Write to FCON FPL3:0 5 User A 5 Extra Row Hardware Security Byte Reset Columns Latches A 5 A 5 A FPS X X X X X X X X FMOD1 0 0 0 0 1 1 1 1 FMOD0 0 0 1 1 0 0 1 1 Operation No action Write the column latches in user space No action Write the column latches in extra row space No action Write the fuse bits space No action Reset the column latches
Notes:
1. The sequence 5xh and Axh must be executing without instructions between them otherwise the programming is not executed (see Flash Status Register) 2. The sequence 5xh and Axh must be executed with the same FMOD0 FMOD1 configuration. 3. Interrupts that may occur during programming time must be disabled to avoid any spurious exit of the programming mode.
Status of the Flash Memory
The bit FBUSY in FCON register is used to indicate the status of programming. FBUSY is set when programming is in progress. The flash programming process is launched the second machine cycle following the sequence 5xh and Axh in FCON. Thus the FBUSY flag should be read by sofware not during the insctruction after the 5xh, Axh sequence but the the second instruction after the 5xh, Axh sequence in FCON (See next example). FBUSY is cleared when the programming is completed.
;*F************************************************************************* ;* NAME: launch_prog ;;*************************************************************************** launch_prog: MOV FCON, #050h MOV FCON #0A0h ; Flash Write Sequence NOP wait_busy: MOV A,FCON JB ACC.0,wait_busy RET ;Required time before reading busy flag
Selecting FM1 Loading the Column Latches
The bit ENBOOT in AUXR1 register is used to map FM1 from F800h to FFFFh. Any number of data from 1-byte to 128 Bytes can be loaded in the column latches. This provides the capability to program the whole memory by byte, by page or by any number of Bytes in a page. Data written in the column latches do not have to be in consecutive
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order. The page address of the last address loaded in the column latches will be used for the whole page. When programming is launched, an automatic erase of the locations loaded in the column latches is first performed, then programming is effectively done. Thus no page or block erase is needed and only the loaded data are programmed in the corresponding page
Notes: 1. : If no bytes are written in the column latches the SEQERR bit in the FSTA register will be set. 2. When a flash write sequence is in progress (FBUSY is set) a write sequence to the column latches will be ignored and the content of the column latches at the time of the launch write sequence will be preserved. 3. MOVX @DPTR, A instruction must be used to load the column latches. Never use MOVX @Ri, A instructions. 4. When a programming sequence is launched, Flash bytes corresponding to activated bytes in the column latches are first erased then the bytes in the column latches are copied into the Flash bytes. Flash bytes corresponding to bytes in the column latches not activated (not loaded during the load column latches sequence) will not be erased and written.
The following procedure is used to load the column latches and is summarized in Figure 25: * * * * * * * Save and Disable interrupt and map the column latch space by setting FPS bit. Load the DPTR with the address to load. Load Accumulator register with the data to load. Execute the MOVX @DPTR, A instruction. If needed loop the three last instructions until the page is completely loaded. unmap the column latch. Restore Interrupt
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Figure 25. Column Latches Loading Procedure
Column Latches Loading
Save and Disable IT EA = 0
Column Latches Mapping FCON = 08h (FPS=1)
Data Load DPTR = Address ACC = Data Exec: MOVX @DPTR, A
Last Byte to load?
Data memory Mapping FCON = 00h (FPS = 0)
Restore IT
Note:
The last page address used when loading the column latch is the one used to select the page programming address.
Programming the Flash Spaces User The following procedure is used to program the User space and is summarized in Figure 26: * * * Load up to one page of data in the column latches from address 0000h to FFFFh. Save and Disable the interrupts. Launch the programming by writing the data sequence 50h followed by A0h in FCON register (only from FM1). The end of the programming indicated by the FBUSY flag cleared. Restore the interrupts.
* Extra Row
The following procedure is used to program the Extra Row space and is summarized in Figure 26: * * * Load data in the column latches from address FF80h to FFFFh. Save and Disable the interrupts. Launch the programming by writing the data sequence 52h followed by A2h in FCON register (only from FM1). The end of the programming indicated by the FBUSY flag cleared. Restore the interrupts. 51
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Figure 26. Flash and Extra Row Programming Procedure
Flash Spaces Programming
Column Latches Loading see Figure 25
Save and Disable IT EA = 0
Launch Programming FCON = 5xh FCON = Axh
FBusy Cleared?
Clear Mode FCON = 00h
End Programming Restore IT
Hardware Security Byte
The following procedure is used to program the Hardware Security Byte space and is summarized in Figure 27:
* * * * * * Set FPS and map Hardware byte (FCON = 0x0C) Save and disable the interrupts. Load DPTR at address 0000h. Load Accumulator register with the data to load. Execute the MOVX @DPTR, A instruction. Launch the programming by writing the data sequence 54h followed by A4h in FCON register (only from FM1). The end of the programming indicated by the FBusy flag cleared. Restore the interrupts.
*
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Figure 27. Hardware Programming Procedure
Flash Spaces Programming
Save and Disable IT EA = 0 Save and Disable IT EA = 0 Launch Programming FCON = 54h FCON = A4h
FCON = 0Ch
Data Load DPTR = 00h ACC = Data Exec: MOVX @DPTR, A
FBusy Cleared?
End Loading Restore IT
Clear Mode FCON = 00h
End Programming RestoreIT
Reset the Column Latches
An automatic reset of the column latches is performed after a successful Flash write sequence. User can also reset the column latches manually, for instance to reload the column latches before writing the Flash. The following procedure is summarized below.
* * * Save and disable the interrupts. Launch the reset by writing the data sequence 56h followed by A6h in FCON register (only from FM1). Restore the interrupts.
Error Reports Flash Programming Sequence Errors When a wrong sequence is detected, the SEQERR bit in FSTA register is set. Possible wrong sequence are : * * * * MOV FCON, 5xh instruction not immediately followed by a MOV FCON, Ax instruction. A write Flash sequence is launched while no data were loaded in the column latches By software By hardware when a correct programming sequence is completed
The SEQERR bit can be cleared
When multiple pages are written into the Flash, the user should check FSTA for errors after each write page sequences, not only at the end of the multiple write pages.
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Power Down Request
Before entering in Power Down (Set bit PD in PCON register) the user should check that no write sequence is in progress (check BUSY=0), then check that the column latches are reset (FLOAD=0 in FSTA register. Launch a reset column latches to clear FLOAD if necessary.
Reading the Flash Spaces User The following procedure is used to read the User space: * Read one byte in Accumulator by executing MOVC A,@A+DPTR with A+DPTR=read@.
FCON is supposed to be reset when not needed.
Note:
Extra Row
The following procedure is used to read the Extra Row space and is summarized in Figure 28: * * * Map the Extra Row space by writing 02h in FCON register. Read one byte in Accumulator by executing MOVC A,@A+DPTR with A = 0 and DPTR = FF80h to FFFFh. Clear FCON to unmap the Extra Row.
Hardware Security Byte
The following procedure is used to read the Hardware Security space and is summarized in Figure 28:
* * Map the Hardware Security space by writing 04h in FCON register. Read the byte in Accumulator by executing MOVC A,@A+DPTR with A = 0 and DPTR = 0000h.
Figure 28. Clear FCON to unmap the Hardware Security Byte.Reading Procedure
Flash Spaces Reading
Flash Spaces Mapping FCON= 00000xx0b
Data Read DPTR= Address ACC= 0 Exec: MOVC A, @A+DPTR
Clear Mode FCON = 00h
Flash Protection from Parallel Programming
The three lock bits in Hardware Security Byte (see "In-System Programming" section) are programmed according to Table 17 provide different level of protection for the onchip code and data located in FM0 and FM1. The only way to write this bits are the parallel mode. They are set by default to level 4
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Table 17. Program Lock Bit
Program Lock Bits Security level 1 LB0 U LB1 U LB2 U Protection Description No program lock features enabled. MOVC instruction executed from external program memory are disabled from fetching code bytes from internal memory, EA is sampled and latched on reset, and further parallel programming of the Flash is disabled. ISP and software programming with API are still allowed. Writing EEprom Data from external parallel programmer is disabled but still allowed from internal code execution. Same as 2, also verify through parallel programming interface is disabled. Writing And Reading EEPROM Data from external parallel programmer is disabled but still allowed from internal code execution.. Same as 3, also external execution is disabled
2
P
U
U
3
U
P
U
4
U
U
P
Program Lock bits U: unprogrammed P: programmed WARNING: Security level 2 and 3 should only be programmed after Flash and Core verification.
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Operation Cross Memory Access
Space addressable in read and write are: * * * * * * * * * RAM ERAM (Expanded RAM access by movx) XRAM (eXternal RAM) EEPROM DATA FM0 ( user flash ) Hardware byte XROW Boot Flash Flash Column latch
The table below provide the different kind of memory which can be accessed from different code location. Table 18. Cross Memory Access
XRAM Action Read boot FLASH Write Read FM0 Write External memory EA = 0 or Code Roll Over Write Read OK (idle) OK RAM ERAM Boot FLASH OK FM0 OK OK(1) OK E Data OK OK(1) OK OK(1) OK OK(1) Hardware Byte OK OK(1) OK XROW OK(1) OK -
Note:
1. RWW: Read While Write
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Sharing Instructions
Table 19. Instructions shared
XRAM Action Read Write RAM MOV MOV ERAM MOVX MOVX EEPROM DATA MOVX MOVX Boot FLASH MOVC FM0 MOVC by cl Hardware Byte MOVC by cl XROW MOVC by cl
Note:
by cl : using Column Latch
Table 20. Read MOVX A, @DPTR
EEE bit in EECON Register 0 0 1 1 FPS in FCON Register 0 1 0 1 ENBOOT X X X X EA X X X X OK XRAM ERAM OK OK OK EEPROM DATA Flash Column Latch
Table 21. Write MOVX @DPTR,A
EEE bit in EECON Register 0 0 1 1 FPS bit in FCON Register 0 1 0 1 ENBOOT X X 0 X X 0 OK X 1 OK OK OK EA X 1 XRAM ERAM OK OK EEPROM Data Flash Column Latch
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Table 22. Read MOVC A, @DPTR
FCON Register Code Execution FMOD1 FMOD0 FPS ENBOOT 0 0 0 X 1 F800h to FFFFh 0 From FM0 1 0 X X 0 1 1 X 1 F800h to FFFFh 0000h to F7FF 1 0 0 0 1 0 From FM1 (ENBOOT =1 0 1 X 0 1 1 0 X 0 1 1 External code : EA=0 or Code Roll Over X 0 X X X OK 1 X 0 000h to FFFFh NA OK X NA 1 X 0000h to 007h See
(2)
Hardware DPTR 0000h to FFFFh 0000h to F7FF FM1 FM0 OK OK Do not use this configuration OK OK OK OK Do not use this configuration OK OK NA OK NA OK NA OK XROW Byte
External Code
1
X
X
0000 to 007Fh See (1) X 000h to FFFFh 0000h to F7FF
F800h to FFFFh 0 1 X X
1. For DPTR higher than 007Fh only lowest 7 bits are decoded, thus the behavior is the same as for addresses from 0000h to 007Fh 2. For DPTR higher than 007Fh only lowest 7 bits are decoded, thus the behavior is the same as for addresses from 0000h to 007Fh
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In-System Programming (ISP)
With the implementation of the User Space (FM0) and the Boot Space (FM1) in Flash technology the AT89C51CC03 allows the system engineer the development of applications with a very high level of flexibility. This flexibility is based on the possibility to alter the customer program at any stages of a product's life: * Before assembly the 1st personalization of the product by programming in the FM0 and if needed also a customized Boot loader in the FM1. Atmel provide also a standard Boot loader by default UART or CAN. After assembling on the PCB in its final embedded position by serial mode via the CAN bus or UART.
*
This In-System Programming (ISP) allows code modification over the total lifetime of the product. Besides the default Boot loader Atmel provide to the customer also all the needed Application-Programming-Interfaces (API) which are needed for the ISP. The API are located also in the Boot memory. This allow the customer to have a full use of the 64-Kbyte user memory.
Flash Programming and Erasure
There are three methods of programming the Flash memory: * The Atmel bootloader located in FM1 is activated by the application. Low level API routines (located in FM1)will be used to program FM0. The interface used for serial downloading to FM0 is the UART or the CAN. API can be called also by the user's bootloader located in FM0 at [SBV]00h. A further method exists in activating the Atmel boot loader by hardware activation. The FM0 can be programmed also by the parallel mode using a programmer.
* *
Figure 29. Flash Memory Mapping FFFFh
Custom Boot Loader [SBV]00h 64K Bytes Flash memory FM0 2K Bytes IAP bootloader FM1
FFFFh
F800h
FM1 mapped between F800h and FFFFh when API called
0000h
Boot Process
Software Boot Process Example Many algorithms can be used for the software boot process. Before describing them, The description of the different flags and Bytes is given below:
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Boot Loader Jump Bit (BLJB): - This bit indicates if on RESET the user wants to jump to this application at address @0000h on FM0 or execute the boot loader at address @F800h on FM1. - BLJB = 0 on parts delivered with bootloader programmed. - To read or modify this bit, the APIs are used. Boot Vector Address (SBV): - This byte contains the MSB of the user boot loader address in FM0. - The default value of SBV is FFh (no user boot loader in FM0). - To read or modify this byte, the APIs are used. Extra Byte (EB) and Boot Status Byte (BSB): - These Bytes are reserved for customer use. - To read or modify these Bytes, the APIs are used.
Hardware Boot Process
At the falling edge of RESET, the bit ENBOOT in AUXR1 register is initialized with the value of Boot Loader Jump Bit (BLJB). Further at the falling edge of RESET if the following conditions (called Hardware condition) are detected: * * * PSEN low, EA high, ALE high (or not connected). - After Hardware Condition the FCON register is initialized with the value 00h and the PC is initialized with F800h (FM1).
The Hardware condition makes the bootloader to be executed, whatever BLJB value is. If no hardware condition is detected, the FCON register is initialized with the value F0h. Check of the BLJB value. * * If bit BLJB = 1: User application in FM0 will be started at @0000h (standard reset). If bit BLJB = 0: Boot loader will be started at @F800h in FM1.
1. As PSEN is an output port in normal operating mode (running user applications or bootloader applications) after reset it is recommended to release PSEN after the falling edge of Reset is signaled. The hardware conditions are sampled at reset signal Falling Edge, thus they can be released at any time when reset input is low. 2. To ensure correct microcontroller startup, the PSEN pin should not be tied to ground during power-on.
Note:
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Figure 30. Hardware Boot Process Algorithm
RESET
bit ENBOOT in AUXR1 register is initialized with BLJB.
Hardware
Hardware condition? No
Yes
ENBOOT = 1 PC = F800h FCON = 00h
ENBOOT = 0 PC = 0000h No
FCON = F0h
BLJB = = 0 ? Yes ENBOOT = 1 PC = F800h
Software
Application in FM0
Boot Loader in FM1
Application Programming Interface
Several Application Program Interface (API) calls are available for use by an application program to permit selective erasing and programming of Flash pages. All calls are made by functions. All these APIs are describe in an documentation: "In-System Programing: Flash Library for AT89C51CC03" available on the Atmel web site.
XROW Bytes
Table 23. XROW Mapping
Description Copy of the Manufacturer Code Copy of the Device ID#1: Family code Copy of the Device ID#2: Memories size and type Copy of the Device ID#3: Name and Revision Default Value 58h D7h FFh FEh Address 30h 31h 60h 61h
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Hardware Security Byte
Table 24. Hardware Security Byte
7 X2B Bit Number 7 6 BLJB 5 4 3 2 LB2 1 LB1 0 LB0
Bit Mnemonic Description X2B X2 Bit Set this bit to start in standard mode Clear this bit to start in X2 mode. Boot Loader JumpBit - 1: To start the user's application on next RESET (@0000h) located in FM0, - 0: To start the boot loader(@F800h) located in FM1. Reserved The value read from these bits are indeterminate. Lock Bits
6
BLJB
5-3 2-0
LB2:0
Default value after erasing chip: FFh
Notes: 1. Only the 4 MSB bits can be accessed by software. 2. The 4 LSB bits can only be accessed by parallel mode.
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Serial I/O Port
The AT89C51CC03 I/O serial port is compatible with the I/O serial port in the 80C52. It provides both synchronous and asynchronous communication modes. It operates as a Universal Asynchronous Receiver and Transmitter (UART) in three full-duplex modes (Modes 1, 2 and 3). Asynchronous transmission and reception can occur simultaneously and at different baud rates Serial I/O port includes the following enhancements: * * Framing error detection Automatic address recognition
Figure 31. Serial I/O Port Block Diagram
IB Bus
Write SBUF SBUF Receiver
Read SBUF
TXD
SBUF Transmitter Mode 0 Transmit
Load SBUF
RXD
Receive Shift register Serial Port Interrupt Request
RI
TI
SCON reg
Framing Error Detection Framing bit error detection is provided for the three asynchronous modes. To enable the
framing bit error detection feature, set SMOD0 bit in PCON register. Figure 32. Framing Error Block Diagram
SM0/FE SM1 SM2 REN TB8 RB8 TI RI
Set FE bit if stop bit is 0 (framing error) SM0 to UART mode control SMOD SMOD0 POF GF1 GF0 PD IDL
To UART framing error control
When this feature is enabled, the receiver checks each incoming data frame for a valid stop bit. An invalid stop bit may result from noise on the serial lines or from simultaneous transmission by two CPUs. If a valid stop bit is not found, the Framing Error bit (FE) in SCON register bit is set. The software may examine the FE bit after each reception to check for data errors. Once set, only software or a reset clears the FE bit. Subsequently received frames with
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valid stop bits cannot clear the FE bit. When the FE feature is enabled, RI rises on the stop bit instead of the last data bit (See Figure 33. and Figure 34.). Figure 33. UART Timing in Mode 1
RXD Start bit RI SMOD0=X FE SMOD0=1 D0 D1 D2 D3 D4 D5 D6 D7 Stop bit
Data byte
Figure 34. UART Timing in Modes 2 and 3
RXD Start bit RI SMOD0=0 RI SMOD0=1 FE SMOD0=1 D0 D1 D2 D3 D4 D5 D6 D7 D8 Ninth Stop bit bit
Data byte
Automatic Address Recognition
The automatic address recognition feature is enabled when the multiprocessor communication feature is enabled (SM2 bit in SCON register is set). Implemented in the hardware, automatic address recognition enhances the multiprocessor communication feature by allowing the serial port to examine the address of each incoming command frame. Only when the serial port recognizes its own address will the receiver set the RI bit in the SCON register to generate an interrupt. This ensures that the CPU is not interrupted by command frames addressed to other devices. If necessary, you can enable the automatic address recognition feature in mode 1. In this configuration, the stop bit takes the place of the ninth data bit. Bit RI is set only when the received command frame address matches the device's address and is terminated by a valid stop bit. To support automatic address recognition, a device is identified by a given address and a broadcast address.
Note: The multiprocessor communication and automatic address recognition features cannot be enabled in mode 0 (i.e. setting SM2 bit in SCON register in mode 0 has no effect).
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Given Address
Each device has an individual address that is specified in the SADDR register; the SADEN register is a mask byte that contains don't-care bits (defined by zeros) to form the device's given address. The don't-care bits provide the flexibility to address one or more slaves at a time. The following example illustrates how a given address is formed. To address a device by its individual address, the SADEN mask byte must be 1111 1111b. For example:
SADDR0101 0110b SADEN1111 1100b Given0101 01XXb
Here is an example of how to use given addresses to address different slaves:
Slave A:SADDR1111 0001b SADEN1111 1010b Given1111 0X0Xb Slave B:SADDR1111 0011b SADEN1111 1001b Given1111 0XX1b Slave C:SADDR1111 0011b SADEN1111 1101b Given1111 00X1b
The SADEN byte is selected so that each slave may be addressed separately. For slave A, bit 0 (the LSB) is a don't-care bit; for slaves B and C, bit 0 is a 1. To communicate with slave A only, the master must send an address where bit 0 is clear (e.g. 1111 0000b). For slave A, bit 1 is a 0; for slaves B and C, bit 1 is a don't care bit. To communicate with slaves A and B, but not slave C, the master must send an address with bits 0 and 1 both set (e.g. 1111 0011b). To communicate with slaves A, B and C, the master must send an address with bit 0 set, bit 1 clear, and bit 2 clear (e.g. 1111 0001b).
Broadcast Address
A broadcast address is formed from the logical OR of the SADDR and SADEN registers with zeros defined as don't-care bits, e.g.:
SADDR0101 0110b SADEN1111 1100b SADDR OR SADEN1111 111Xb
The use of don't-care bits provides flexibility in defining the broadcast address, however in most applications, a broadcast address is FFh. The following is an example of using broadcast addresses:
Slave A:SADDR1111 0001b SADEN1111 1010b Given1111 1X11b, Slave B:SADDR1111 0011b SADEN1111 1001b Given1111 1X11B, Slave C:SADDR=1111 0010b SADEN1111 1101b Given1111 1111b
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For slaves A and B, bit 2 is a don't care bit; for slave C, bit 2 is set. To communicate with all of the slaves, the master must send an address FFh. To communicate with slaves A and B, but not slave C, the master can send and address FBh.
Registers
Table 25. SCON Register SCON (S:98h) Serial Control Register
7 FE/SM0 Bit Number 7 6 SM1 5 SM2 4 REN 3 TB8 2 RB8 1 TI 0 RI
Bit Mnemonic Description FE Framing Error bit (SMOD0=1) Clear to reset the error state, not cleared by a valid stop bit. Set by hardware when an invalid stop bit is detected. Serial port Mode bit 0 (SMOD0=0) Refer to SM1 for serial port mode selection. Serial port Mode bit 1 SM0 SM1 Mode 0 0 Shift Register 0 1 8-bit UART 1 0 9-bit UART 1 1 9-bit UART Baud Rate FXTAL/12 (or FXTAL /6 in mode X2) Variable FXTAL/64 or FXTAL/32 Variable
SM0
6
SM1
5
SM2
Serial port Mode 2 bit/Multiprocessor Communication Enable bit Clear to disable multiprocessor communication feature. Set to enable multiprocessor communication feature in mode 2 and 3. Reception Enable bit Clear to disable serial reception. Set to enable serial reception. Transmitter Bit 8/Ninth bit to transmit in modes 2 and 3 Clear to transmit a logic 0 in the 9th bit. Set to transmit a logic 1 in the 9th bit. Receiver Bit 8/Ninth bit received in modes 2 and 3 Cleared by hardware if 9th bit received is a logic 0. Set by hardware if 9th bit received is a logic 1. Transmit Interrupt flag Clear to acknowledge interrupt. Set by hardware at the end of the 8th bit time in mode 0 or at the beginning of the stop bit in the other modes. Receive Interrupt flag Clear to acknowledge interrupt. Set by hardware at the end of the 8th bit time in mode 0, see Figure 33. and Figure 34. in the other modes.
4
REN
3
TB8
2
RB8
1
TI
0
RI
Reset Value = 0000 0000b Bit addressable
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Table 26. SADEN Register SADEN (S:B9h) Slave Address Mask Register
7 - Bit Number 7-0 6 - 5 - 4 - 3 - 2 - 1 - 0 -
Bit Mnemonic Description Mask Data for Slave Individual Address
Reset Value = 0000 0000b Not bit addressable Table 27. SADDR Register SADDR (S:A9h) Slave Address Register
7 - Bit Number 7-0 6 - 5 - 4 - 3 - 2 - 1 - 0 -
Bit Mnemonic Description Slave Individual Address
Reset Value = 0000 0000b Not bit addressable Table 28. SBUF Register SBUF (S:99h) Serial Data Buffer
7 - Bit Number 7-0 6 - 5 - 4 - 3 - 2 - 1 - 0 -
Bit Mnemonic Description Data sent/received by Serial I/O Port
Reset Value = 0000 0000b Not bit addressable
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Table 29. PCON Register PCON (S:87h) Power Control Register
7 SMOD1 Bit Number 7 6 SMOD0 5 - 4 POF 3 GF1 2 GF0 1 PD 0 IDL
Bit Mnemonic Description SMOD1 Serial port Mode bit 1 Set to select double baud rate in mode 1, 2 or 3. Serial port Mode bit 0 Clear to select SM0 bit in SCON register. Set to select FE bit in SCON register. Reserved The value read from this bit is indeterminate. Do not set this bit. Power-Off Flag Clear to recognize next reset type. Set by hardware when VCC rises from 0 to its nominal voltage. Can also be set by software. General-purpose Flag Cleared by user for general-purpose usage. Set by user for general-purpose usage. General-purpose Flag Cleared by user for general-purpose usage. Set by user for general-purpose usage. Power-Down mode bit Cleared by hardware when reset occurs. Set to enter power-down mode. Idle mode bit Clear by hardware when interrupt or reset occurs. Set to enter idle mode.
6
SMOD0
5
-
4
POF
3
GF1
2
GF0
1
PD
0
IDL
Reset Value = 00X1 0000b Not bit addressable
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Timers/Counters
The AT89C51CC03 implements two general-purpose, 16-bit Timers/Counters. Such are identified as Timer 0 and Timer 1, and can be independently configured to operate in a variety of modes as a Timer or an event Counter. When operating as a Timer, the Timer/Counter runs for a programmed length of time, then issues an interrupt request. When operating as a Counter, the Timer/Counter counts negative transitions on an external pin. After a preset number of counts, the Counter issues an interrupt request. The various operating modes of each Timer/Counter are described in the following sections. A basic operation is Timer registers THx and TLx (x = 0, 1) connected in cascade to form a 16-bit Timer. Setting the run control bit (TRx) in TCON register (see Figure 30) turns the Timer on by allowing the selected input to increment TLx. When TLx overflows it increments THx; when THx overflows it sets the Timer overflow flag (TFx) in TCON register. Setting the TRx does not clear the THx and TLx Timer registers. Timer registers can be accessed to obtain the current count or to enter preset values. They can be read at any time but TRx bit must be cleared to preset their values, otherwise the behavior of the Timer/Counter is unpredictable. The C/Tx# control bit selects Timer operation or Counter operation by selecting the divided-down peripheral clock or external pin Tx as the source for the counted signal. TRx bit must be cleared when changing the mode of operation, otherwise the behavior of the Timer/Counter is unpredictable. For Timer operation (C/Tx# = 0), the Timer register counts the divided-down peripheral clock. The Timer register is incremented once every peripheral cycle (6 peripheral clock periods). The Timer clock rate is FPER/6, i.e. FOSC/12 in standard mode or FOSC/6 in X2 mode. For Counter operation (C/Tx# = 1), the Timer register counts the negative transitions on the Tx external input pin. The external input is sampled every peripheral cycles. When the sample is high in one cycle and low in the next one, the Counter is incremented. Since it takes 2 cycles (12 peripheral clock periods) to recognize a negative transition, the maximum count rate is FPER/12, i.e. FOSC/24 in standard mode or F OSC/12 in X2 mode. There are no restrictions on the duty cycle of the external input signal, but to ensure that a given level is sampled at least once before it changes, it should be held for at least one full peripheral cycle.
Timer/Counter Operations
Timer 0
Timer 0 functions as either a Timer or event Counter in four modes of operation. Figure 35 to Figure 38 show the logical configuration of each mode. Timer 0 is controlled by the four lower bits of TMOD register (see Figure 31) and bits 0, 1, 4 and 5 of TCON register (see Figure 30). TMOD register selects the method of Timer gating (GATE0), Timer or Counter operation (T/C0#) and mode of operation (M10 and M00). TCON register provides Timer 0 control functions: overflow flag (TF0), run control bit (TR0), interrupt flag (IE0) and interrupt type control bit (IT0). For normal Timer operation (GATE0 = 0), setting TR0 allows TL0 to be incremented by the selected input. Setting GATE0 and TR0 allows external pin INT0# to control Timer operation. Timer 0 overflow (count rolls over from all 1s to all 0s) sets TF0 flag generating an interrupt request. It is important to stop Timer/Counter before changing mode.
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Mode 0 (13-bit Timer)
Mode 0 configures Timer 0 as an 13-bit Timer which is set up as an 8-bit Timer (TH0 register) with a modulo 32 prescaler implemented with the lower five bits of TL0 register (see Figure 35). The upper three bits of TL0 register are indeterminate and should be ignored. Prescaler overflow increments TH0 register.
Figure 35. Timer/Counter x (x = 0 or 1) in Mode 0
See the "Clock" section
FTx CLOCK /6 0 1
THx (8 bits)
TLx (5 bits)
Overflow
TFx
TCON reg
Tx
Timer x Interrupt Request
C/Tx#
TMOD reg
INTx# GATEx
TMOD reg
TRx
TCON reg
Mode 1 (16-bit Timer)
Mode 1 configures Timer 0 as a 16-bit Timer with TH0 and TL0 registers connected in cascade (see Figure 36). The selected input increments TL0 register.
Figure 36. Timer/Counter x (x = 0 or 1) in Mode 1
See the "Clock" section
FTx CLOCK /6 0 1
THx (8 bits)
TLx (8 bits)
Overflow
TFx
TCON reg
Tx
Timer x Interrupt Request
C/Tx#
TMOD reg
INTx# GATEx
TMOD reg
TRx
TCON reg
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Mode 2 (8-bit Timer with Auto- Mode 2 configures Timer 0 as an 8-bit Timer (TL0 register) that automatically reloads Reload) from TH0 register (see Figure 37). TL0 overflow sets TF0 flag in TCON register and reloads TL0 with the contents of TH0, which is preset by software. When the interrupt request is serviced, hardware clears TF0. The reload leaves TH0 unchanged. The next reload value may be changed at any time by writing it to TH0 register. Figure 37. Timer/Counter x (x = 0 or 1) in Mode 2
See the "Clock" section
FTx CLOCK /6 0 1
TLx (8 bits)
Overflow
TFx
TCON reg
Tx
Timer x Interrupt Request
C/Tx#
TMOD reg
INTx# GATEx
TMOD reg
TRx
TCON reg
THx (8 bits)
Mode 3 (Two 8-bit Timers)
Mode 3 configures Timer 0 such that registers TL0 and TH0 operate as separate 8-bit Timers (see Figure 38). This mode is provided for applications requiring an additional 8bit Timer or Counter. TL0 uses the Timer 0 control bits C/T0# and GATE0 in TMOD register, and TR0 and TF0 in TCON register in the normal manner. TH0 is locked into a Timer function (counting FPER /6) and takes over use of the Timer 1 interrupt (TF1) and run control (TR1) bits. Thus, operation of Timer 1 is restricted when Timer 0 is in mode 3.
Figure 38. Timer/Counter 0 in Mode 3: Two 8-bit Counters
FTx CLOCK /6 0 1
TL0 (8 bits)
Overflow
TF0
TCON.5
T0
Timer 0 Interrupt Request
C/T0#
TMOD.2
INT0# GATE0
TMOD.3
TR0
TCON.4
FTx CLOCK
/6
TH0 (8 bits) TR1
TCON.6
Overflow
TF1
TCON.7
Timer 1 Interrupt Request
See the "Clock" section
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Timer 1
Timer 1 is identical to Timer 0 excepted for Mode 3 which is a hold-count mode. The following comments help to understand the differences: * Timer 1 functions as either a Timer or event Counter in three modes of operation. Figure 35 to Figure 37 show the logical configuration for modes 0, 1, and 2. Timer 1's mode 3 is a hold-count mode. Timer 1 is controlled by the four high-order bits of TMOD register (see Figure 31) and bits 2, 3, 6 and 7 of TCON register (see Figure 30). TMOD register selects the method of Timer gating (GATE1), Timer or Counter operation (C/T1#) and mode of operation (M11 and M01). TCON register provides Timer 1 control functions: overflow flag (TF1), run control bit (TR1), interrupt flag (IE1) and interrupt type control bit (IT1). Timer 1 can serve as the Baud Rate Generator for the Serial Port. Mode 2 is best suited for this purpose. For normal Timer operation (GATE1 = 0), setting TR1 allows TL1 to be incremented by the selected input. Setting GATE1 and TR1 allows external pin INT1# to control Timer operation. Timer 1 overflow (count rolls over from all 1s to all 0s) sets the TF1 flag generating an interrupt request. When Timer 0 is in mode 3, it uses Timer 1's overflow flag (TF1) and run control bit (TR1). For this situation, use Timer 1 only for applications that do not require an interrupt (such as a Baud Rate Generator for the Serial Port) and switch Timer 1 in and out of mode 3 to turn it off and on. It is important to stop Timer/Counter before changing mode.
*
* *
* *
* Mode 0 (13-bit Timer)
Mode 0 configures Timer 1 as a 13-bit Timer, which is set up as an 8-bit Timer (TH1 register) with a modulo-32 prescaler implemented with the lower 5 bits of the TL1 register (see Figure 35). The upper 3 bits of TL1 register are ignored. Prescaler overflow increments TH1 register. Mode 1 configures Timer 1 as a 16-bit Timer with TH1 and TL1 registers connected in cascade (see Figure 36). The selected input increments TL1 register.
Mode 1 (16-bit Timer)
Mode 2 (8-bit Timer with Auto- Mode 2 configures Timer 1 as an 8-bit Timer (TL1 register) with automatic reload from Reload) TH1 register on overflow (see Figure 37). TL1 overflow sets TF1 flag in TCON register and reloads TL1 with the contents of TH1, which is preset by software. The reload leaves TH1 unchanged. Mode 3 (Halt) Placing Timer 1 in mode 3 causes it to halt and hold its count. This can be used to halt Timer 1 when TR1 run control bit is not available i.e. when Timer 0 is in mode 3.
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Interrupt
Each Timer handles one interrupt source that is the timer overflow flag TF0 or TF1. This flag is set every time an overflow occurs. Flags are cleared when vectoring to the Timer interrupt routine. Interrupts are enabled by setting ETx bit in IEN0 register. This assumes interrupts are globally enabled by setting EA bit in IEN0 register. Figure 39. Timer Interrupt System
TF0
TCON.5
Timer 0 Interrupt Request ET0
IEN0.1
TF1
TCON.7
Timer 1 Interrupt Request ET1
IEN0.3
Registers
Table 30. TCON Register TCON (S:88h) Timer/Counter Control Register
7 TF1 Bit Number 7 6 TR1 5 TF0 4 TR0 3 IE1 2 IT1 1 IE0 0 IT0
Bit Mnemonic Description TF1 Timer 1 Overflow Flag Cleared by hardware when processor vectors to interrupt routine. Set by hardware on Timer/Counter overflow, when Timer 1 register overflows. Timer 1 Run Control Bit Clear to turn off Timer/Counter 1. Set to turn on Timer/Counter 1. Timer 0 Overflow Flag Cleared by hardware when processor vectors to interrupt routine. Set by hardware on Timer/Counter overflow, when Timer 0 register overflows. Timer 0 Run Control Bit Clear to turn off Timer/Counter 0. Set to turn on Timer/Counter 0. Interrupt 1 Edge Flag Cleared by hardware when interrupt is processed if edge-triggered (see IT1). Set by hardware when external interrupt is detected on INT1# pin. Interrupt 1 Type Control Bit Clear to select low level active (level triggered) for external interrupt 1 (INT1#). Set to select falling edge active (edge triggered) for external interrupt 1. Interrupt 0 Edge Flag Cleared by hardware when interrupt is processed if edge-triggered (see IT0). Set by hardware when external interrupt is detected on INT0# pin. Interrupt 0 Type Control Bit Clear to select low level active (level triggered) for external interrupt 0 (INT0#). Set to select falling edge active (edge triggered) for external interrupt 0.
6
TR1
5
TF0
4
TR0
3
IE1
2
IT1
1
IE0
0
IT0
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Table 31. TMOD Register TMOD (S:89h) Timer/Counter Mode Control Register
7 GATE1 Bit Number 7 6 C/T1# 5 M11 4 M01 3 GATE0 2 C/T0# 1 M10 0 M00
Bit Mnemonic Description GATE1 Timer 1 Gating Control Bit Clear to enable Timer 1 whenever TR1 bit is set. Set to enable Timer 1 only while INT1# pin is high and TR1 bit is set. Timer 1 Counter/Timer Select Bit Clear for Timer operation: Timer 1 counts the divided-down system clock. Set for Counter operation: Timer 1 counts negative transitions on external pin T1. Timer 1 Mode Select Bits M11 M01 Operating mode 0 0 Mode 0: 8-bit Timer/Counter (TH1) with 5-bit prescaler (TL1). 0 1 Mode 1: 16-bit Timer/Counter. 1 0 Mode 2: 8-bit auto-reload Timer/Counter (TL1) (1) 1 1 Mode 3: Timer 1 halted. Retains count Timer 0 Gating Control Bit Clear to enable Timer 0 whenever TR0 bit is set. Set to enable Timer/Counter 0 only while INT0# pin is high and TR0 bit is set. Timer 0 Counter/Timer Select Bit Clear for Timer operation: Timer 0 counts the divided-down system clock. Set for Counter operation: Timer 0 counts negative transitions on external pin T0. Timer 0 Mode Select Bit Operating mode M10 M00 0 0 Mode 0: 8-bit Timer/Counter (TH0) with 5-bit prescaler (TL0). 0 1 Mode 1: 16-bit Timer/Counter. 1 0 Mode 2: 8-bit auto-reload Timer/Counter (TL0) (2) 1 1 Mode 3: TL0 is an 8-bit Timer/Counter TH0 is an 8-bit Timer using Timer 1's TR0 and TF0 bits.
6 5
C/T1# M11
4
M01
3
GATE0
2
C/T0#
1
M10
0
M00
1.
Reloaded from TH1 at overflow.
2.
Reloaded from TH0 at overflow.
Reset Value = 0000 0000b
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Table 32. TH0 Register TH0 (S:8Ch) Timer 0 High Byte Register
7 - Bit Number 7:0 6 - 5 - 4 - 3 - 2 - 1 - 0 -
Bit Mnemonic Description High Byte of Timer 0.
Reset Value = 0000 0000b Table 33. TL0 Register TL0 (S:8Ah) Timer 0 Low Byte Register
7 - Bit Number 7:0 6 - 5 - 4 - 3 - 2 - 1 - 0 -
Bit Mnemonic Description Low Byte of Timer 0.
Reset Value = 0000 0000b Table 34. TH1 Register TH1 (S:8Dh) Timer 1 High Byte Register
7 - Bit Number 7:0 6 - 5 - 4 - 3 - 2 - 1 - 0 -
Bit Mnemonic Description High Byte of Timer 1.
Reset Value = 0000 0000b
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Table 35. TL1 Register TL1 (S:8Bh) Timer 1 Low Byte Register
7 - Bit Number 7:0 6 - 5 - 4 - 3 - 2 - 1 - 0 -
Bit Mnemonic Description Low Byte of Timer 1.
Reset Value = 0000 0000b
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Timer 2
The AT89C51CC03 timer 2 is compatible with timer 2 in the 80C52. It is a 16-bit timer/counter: the count is maintained by two eight-bit timer registers, TH2 and TL2 that are cascade- connected. It is controlled by T2CON register (See Table ) and T2MOD register (See Table 38). Timer 2 operation is similar to Timer 0 and Timer 1. C/T2 selects FT2 clock/6 (timer operation) or external pin T2 (counter operation) as timer clock. Setting TR2 allows TL2 to be incremented by the selected input. Timer 2 includes the following enhancements: * * Auto-reload mode (up or down counter) Programmable clock-output
Auto-Reload Mode
The auto-reload mode configures timer 2 as a 16-bit timer or event counter with automatic reload. This feature is controlled by the DCEN bit in T2MOD register (See Table 38). Setting the DCEN bit enables timer 2 to count up or down as shown in Figure 40. In this mode the T2EX pin controls the counting direction. When T2EX is high, timer 2 counts up. Timer overflow occurs at FFFFh which sets the TF2 flag and generates an interrupt request. The overflow also causes the 16-bit value in RCAP2H and RCAP2L registers to be loaded into the timer registers TH2 and TL2. When T2EX is low, timer 2 counts down. Timer underflow occurs when the count in the timer registers TH2 and TL2 equals the value stored in RCAP2H and RCAP2L registers. The underflow sets TF2 flag and reloads FFFFh into the timer registers. The EXF2 bit toggles when timer 2 overflow or underflow, depending on the direction of the count. EXF2 does not generate an interrupt. This bit can be used to provide 17-bit resolution.
Figure 40. Auto-Reload Mode Up/Down Counter
see section "Clock"
FT2 CLOCK :6 0 1
TR2 CT/2
T2CON.1 T2CON.2
T2 (DOWN COUNTING RELOAD VALUE) FFh (8-bit) T2EX: 1=UP 2=DOWN TOGGLE T2CONreg EXF2 TL2 (8-bit) TH2 (8-bit) TF2 T2CONreg TIMER 2 INTERRUPT
(8-bit)
FFh
RCAP2L (8-bit)
RCAP2H (8-bit)
(UP COUNTING RELOAD VALUE)
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Programmable ClockOutput
In clock-out mode, timer 2 operates as a 50%-duty-cycle, programmable clock generator (See Figure 41). The input clock increments TL2 at frequency FOSC/2. The timer repeatedly counts to overflow from a loaded value. At overflow, the contents of RCAP2H and RCAP2L registers are loaded into TH2 and TL2. In this mode, timer 2 overflows do not generate interrupts. The formula gives the clock-out frequency depending on the system oscillator frequency and the value in the RCAP2H and RCAP2L registers:
FT2clock Clock - OutFrequency = ---------------------------------------------------------------------------------------4 x ( 65536 - RCAP2H RCAP2L ) For a 16 MHz system clock in x1 mode, timer 2 has a programmable frequency range of 61 Hz (FOSC/216) to 4 MHz (FOSC/4). The generated clock signal is brought out to T2 pin (P1.0). Timer 2 is programmed for the clock-out mode as follows: * * * * * Set T2OE bit in T2MOD register. Clear C/T2 bit in T2CON register. Determine the 16-bit reload value from the formula and enter it in RCAP2H/RCAP2L registers. Enter a 16-bit initial value in timer registers TH2/TL2. It can be the same as the reload value or different depending on the application. To start the timer, set TR2 run control bit in T2CON register.
It is possible to use timer 2 as a baud rate generator and a clock generator simultaneously. For this configuration, the baud rates and clock frequencies are not independent since both functions use the values in the RCAP2H and RCAP2L registers. Figure 41. Clock-Out Mode
FT2 CLOCK
TL2 (8-bit)
TH2 (8-bit) OVERFLOW
TR2
T2CON.2
RCAP2L RCAP2H (8-bit) (8-bit) Toggle T2 Q Q D T2OE T2MOD reg
T2EX EXEN2 T2CON reg
EXF2 T2CON reg
TIMER 2 INTERRUPT
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Registers
Table 36. T2CON Register T2CON (S:C8h) Timer 2 Control Register
7 TF2 Bit Number 6 EXF2 5 RCLK 4 TCLK 3 EXEN2 2 TR2 1 C/T2# 0 CP/RL2#
Bit Mnemonic Description Timer 2 Overflow Flag TF2 is not set if RCLK=1 or TCLK = 1. Must be cleared by software. Set by hardware on timer 2 overflow. Timer 2 External Flag Set when a capture or a reload is caused by a negative transition on T2EX pin if EXEN2=1. Set to cause the CPU to vector to timer 2 interrupt routine when timer 2 interrupt is enabled. Must be cleared by software. Receive Clock bit Clear to use timer 1 overflow as receive clock for serial port in mode 1 or 3. Set to use timer 2 overflow as receive clock for serial port in mode 1 or 3. Transmit Clock bit Clear to use timer 1 overflow as transmit clock for serial port in mode 1 or 3. Set to use timer 2 overflow as transmit clock for serial port in mode 1 or 3. Timer 2 External Enable bit Clear to ignore events on T2EX pin for timer 2 operation. Set to cause a capture or reload when a negative transition on T2EX pin is detected, if timer 2 is not used to clock the serial port. Timer 2 Run Control bit Clear to turn off timer 2. Set to turn on timer 2. Timer/Counter 2 Select bit Clear for timer operation (input from internal clock system: FOSC). Set for counter operation (input from T2 input pin). Timer 2 Capture/Reload bit If RCLK=1 or TCLK=1, CP/RL2# is ignored and timer is forced to auto-reload on timer 2 overflow. Clear to auto-reload on timer 2 overflows or negative transitions on T2EX pin if EXEN2=1. Set to capture on negative transitions on T2EX pin if EXEN2=1.
7
TF2
6
EXF2
5
RCLK
4
TCLK
3
EXEN2
2
TR2
1
C/T2#
0
CP/RL2#
Reset Value = 0000 0000b Bit addressable
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Table 37. T2MOD Register T2MOD (S:C9h) Timer 2 Mode Control Register
7 Bit Number 7 6 5 4 3 2 6 5 4 3 2 1 T2OE 0 DCEN
Bit Mnemonic Description Reserved The value read from this bit is indeterminate. Do not set this bit. Reserved The value read from this bit is indeterminate. Do not set this bit. Reserved The value read from this bit is indeterminate. Do not set this bit. Reserved The value read from this bit is indeterminate. Do not set this bit. Reserved The value read from this bit is indeterminate. Do not set this bit. Reserved The value read from this bit is indeterminate. Do not set this bit. Timer 2 Output Enable bit Clear to program P1.0/T2 as clock input or I/O port. Set to program P1.0/T2 as clock output. Down Counter Enable bit Clear to disable timer 2 as up/down counter. Set to enable timer 2 as up/down counter.
1
T2OE
0
DCEN
Reset Value = XXXX XX00b Not bit addressable Table 38. TH2 Register TH2 (S:CDh) Timer 2 High Byte Register
7 Bit Number 7-0 6 5 4 3 2 1 0 -
Bit Mnemonic Description High Byte of Timer 2.
Reset Value = 0000 0000b Not bit addressable
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Table 39. TL2 Register TL2 (S:CCh) Timer 2 Low Byte Register
7 Bit Number 7-0 6 5 4 3 2 1 0 -
Bit Mnemonic Description Low Byte of Timer 2.
Reset Value = 0000 0000b Not bit addressable Table 40. RCAP2H Register RCAP2H (S:CBh) Timer 2 Reload/Capture High Byte Register
7 Bit Number 7-0 6 5 4 3 2 1 0 -
Bit Mnemonic Description High Byte of Timer 2 Reload/Capture.
Reset Value = 0000 0000b Not bit addressable Table 41. RCAP2L Register RCAP2L (S:CAH) TIMER 2 REload/Capture Low Byte Register
7 Bit Number 7-0 6 5 4 3 2 1 0 -
Bit Mnemonic Description Low Byte of Timer 2 Reload/Capture.
Reset Value = 0000 0000b Not bit addressable
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Watchdog Timer
AT89C51CC03 contains a powerful programmable hardware Watchdog Timer (WDT) that automatically resets the chip if it software fails to reset the WDT before the selected time interval has elapsed. It permits large Time-Out ranking from 16ms to 2s @Fosc = 12MHz in X1 mode. This WDT consists of a 14-bit counter plus a 7-bit programmable counter, a Watchdog Timer reset register (WDTRST) and a Watchdog Timer programming (WDTPRG) register. When exiting reset, the WDT is -by default- disable. To enable the WDT, the user has to write the sequence 1EH and E1H into WDTRST register no instruction in between. When the Watchdog Timer is enabled, it will increment every machine cycle while the oscillator is running and there is no way to disable the WDT except through reset (either hardware reset or WDT overflow reset). When WDT overflows, it will generate an output RESET pulse at the RST pin. The RESET pulse duration is 96xTOSC, where TOSC=1/FOSC. To make the best use of the WDT, it should be serviced in those sections of code that will periodically be executed within the time required to prevent a WDT reset
Note: When the Watchdog is enable it is impossible to change its period.
Figure 42. Watchdog Timer
Fwd CLOCK / PS /6 CPU and Peripheral Clock
RESET WR WDTRST
Decoder
Control
Enable 14-bit COUNTER Fwd Clock WDTPRG Outputs 7-bit COUNTER
-
-
-
-
-
2
1
0 RESET
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Watchdog Programming
The three lower bits (S0, S1, S2) located into WDTPRG register permit to program the WDT duration. Table 42. Machine Cycle Count
S2 0 0 0 0 1 1 1 1 S1 0 0 1 1 0 0 1 1 S0 0 1 0 1 0 1 0 1 Machine Cycle Count 214 215 216 217 218 219 220 221
To compute WD Time-Out, the following formula is applied: F wd FTime - Out = ---------------------------------------------------------------------------WDX2 X2 14 Svalue 6x2 (2 x 2 )
Note: Svalue represents the decimal value of (S2 S1 S0)
The following table outlines the time-out value for FoscXTAL = 12 MHz in X1 mode Table 43. Time-Out Computation
S2 0 0 0 0 1 1 1 1 S1 0 0 1 1 0 0 1 1 S0 0 1 0 1 0 1 0 1 Fosc = 12 MHz 16.38 ms 32.77 ms 65.54 ms 131.07 ms 262.14 ms 524.29 ms 1.05 s 2.10 s Fosc = 16 MHz 12.28 ms 24.57 ms 49.14 ms 98.28 ms 196.56 ms 393.12 ms 786.24 ms 1.57 s Fosc = 20 MHz 9.82 ms 19.66 ms 39.32 ms 78.64 ms 157.28 ms 314.56 ms 629.12 ms 1.25 s
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Watchdog Timer During Power-down Mode and Idle
In Power-down mode the oscillator stops, which means the WDT also stops. While in Power-down mode, the user does not need to service the WDT. There are 2 methods of exiting Power-down mode: by a hardware reset or via a level activated external interrupt which is enabled prior to entering Power-down mode. When Power-down is exited with hardware reset, the Watchdog is disabled. Exiting Power-down with an interrupt is significantly different. The interrupt shall be held low long enough for the oscillator to stabilize. When the interrupt is brought high, the interrupt is serviced. To prevent the WDT from resetting the device while the interrupt pin is held low, the WDT is not started until the interrupt is pulled high. It is suggested that the WDT be reset during the interrupt service for the interrupt used to exit Power-down. To ensure that the WDT does not overflow within a few states of exiting powerdown, it is best to reset the WDT just before entering powerdown. In the Idle mode, the oscillator continues to run. To prevent the WDT from resetting AT89C51CC03 while in Idle mode, the user should always set up a timer that will periodically exit Idle, service the WDT, and re-enter Idle mode.
Register
Table 44. WDTPRG Register WDTPRG (S:A7h) Watchdog Timer Duration Programming Register
7 - Bit Number 7 6 5 4 3 2 1 0 6 - 5 - 4 - 3 - 2 S2 1 S1 0 S0
Bit Mnemonic Description S2 S1 S0 Reserved The value read from this bit is indeterminate. Do not set this bit. Reserved The value read from this bit is indeterminate. Do not set this bit. Reserved The value read from this bit is indeterminate. Do not set this bit. Reserved The value read from this bit is indeterminate. Do not set this bit. Reserved The value read from this bit is indeterminate. Do not set this bit. Watchdog Timer Duration selection bit 2 Work in conjunction with bit 1 and bit 0. Watchdog Timer Duration selection bit 1 Work in conjunction with bit 2 and bit 0. Watchdog Timer Duration selection bit 0 Work in conjunction with bit 1 and bit 2.
Reset Value = XXXX X000b
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Table 45. WDTRST Register WDTRST (S:A6h Write only) Watchdog Timer Enable Register
7 - Bit Number 7 6 - 5 - 4 - 3 - 2 - 1 - 0 -
Bit Mnemonic Description Watchdog Control Value
Reset Value = 1111 1111b
Note: The WDRST register is used to reset/enable the WDT by writing 1EH then E1H in sequence without instruction between these two sequences.
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CAN Controller
The CAN Controller provides all the features required to implement the serial communication protocol CAN as defined by BOSCH GmbH. The CAN specification as referred to by ISO/11898 (2.0A and 2.0B) for high speed and ISO/11519-2 for low speed. The CAN Controller is able to handle all types of frames (Data, Remote, Error and Overload) and achieves a bitrate of 1-Mbit/sec at 8 MHz1 Crystal frequency in X2 mode.
Note: 1. At BRP = 1 sampling point will be fixed.
CAN Protocol
Principles
The CAN protocol is an international standard defined in the ISO 11898 for high speed and ISO 11519-2 for low speed. CAN is based on a broadcast communication mechanism. This broadcast communication is achieved by using a message oriented transmission protocol. These messages are identified by using a message identifier. Such a message identifier has to be unique within the whole network and it defines not only the content but also the priority of the message. The priority at which a message is transmitted compared to another less urgent message is specified by the identifier of each message. The priorities are laid down during system design in the form of corresponding binary values and cannot be changed dynamically. The identifier with the lowest binary number has the highest priority. Bus access conflicts are resolved by bit-wise arbitration on the identifiers involved by each node observing the bus level bit for bit. This happens in accordance with the "wired and" mechanism, by which the dominant state overwrites the recessive state. The competition for bus allocation is lost by all nodes with recessive transmission and dominant observation. All the "losers" automatically become receivers of the message with the highest priority and do not re-attempt transmission until the bus is available again.
Message Formats
The CAN protocol supports two message frame formats, the only essential difference being in the length of the identifier. The CAN standard frame, also known as CAN 2.0 A, supports a length of 11 bits for the identifier, and the CAN extended frame, also known as CAN 2.0 B, supports a length of 29 bits for the identifier.
Can Standard Frame Figure 43. CAN Standard Frames
Data Frame
Bus Idle SOF 11-bit identifier ID10..0 RTR IDE r0 4-bit DLC DLC4..0 0 - 8 bytes 15-bit CRC CRC ACK del. ACK del. 7 bits Intermission 3 bits Bus Idle (Indefinite)
Interframe Space
Arbitration Field
Control Field
Data Field
CRC Field
ACK Field
End of Frame
Interframe Space
Remote Frame
Bus Idle SOF 11-bit identifier ID10..0 RTR IDE r0 4-bit DLC DLC4..0 15-bit CRC CRC ACK del. ACK del. 7 bits Intermission 3 bits Bus Idle (Indefinite)
Interframe Space
Arbitration Field
Control Field
CRC Field
ACK Field
End of Frame
Interframe Space
A message in the CAN standard frame format begins with the "Start Of Frame (SOF)", this is followed by the "Arbitration field" which consist of the identifier and the "Remote Transmission Request (RTR)" bit used to distinguish between the data frame and the data request frame called remote frame. The following "Control field" contains the "IDentifier Extension (IDE)" bit and the "Data Length Code (DLC)" used to indicate the 86
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number of following data bytes in the "Data field". In a remote frame, the DLC contains the number of requested data bytes. The "Data field" that follows can hold up to 8 data bytes. The frame integrity is guaranteed by the following "Cyclic Redundant Check (CRC)" sum. The "ACKnowledge (ACK) field" compromises the ACK slot and the ACK delimiter. The bit in the ACK slot is sent as a recessive bit and is overwritten as a dominant bit by the receivers which have at this time received the data correctly. Correct messages are acknowledged by the receivers regardless of the result of the acceptance test. The end of the message is indicated by "End Of Frame (EOF)". The "Intermission Frame Space (IFS)" is the minimum number of bits separating consecutive messages. If there is no following bus access by any node, the bus remains idle. CAN Extended Frame Figure 44. CAN Extended Frames
Data Frame
Bus Idle SOF 11-bit base identifier IDT28..18 SRR IDE 18-bit identifier extension ID17..0 RTR r1 r0 4-bit DLC DLC4..0 0 - 8 bytes 15-bit CRC CRC ACK del. ACK del. 7 bits Intermission Bus Idle 3 bits (Indefinite)
Interframe Space
Arbitration Field
Control Field
Data Field
CRC Field
ACK Field
End of Frame
Interframe Space
Remote Frame
Bus Idle SOF 11-bit base identifier IDT28..18 SRR IDE 18-bit identifier extension ID17..0 RTR r1 r0 4-bit DLC DLC4..0 15-bit CRC CRC ACK del. ACK del. 7 bits Intermission 3 bits Bus Idle (Indefinite)
Interframe Space
Arbitration Field
Control Field
CRC Field
ACK Field
End of Frame
Interframe Space
A message in the CAN extended frame format is likely the same as a message in CAN standard frame format. The difference is the length of the identifier used. The identifier is made up of the existing 11-bit identifier (base identifier) and an 18-bit extension (identifier extension). The distinction between CAN standard frame format and CAN extended frame format is made by using the IDE bit which is transmitted as dominant in case of a frame in CAN standard frame format, and transmitted as recessive in the other case. Format Co-existence As the two formats have to co-exist on one bus, it is laid down which message has higher priority on the bus in the case of bus access collision with different formats and the same identifier / base identifier: The message in CAN standard frame format always has priority over the message in extended format. There are three different types of CAN modules available: - - - Bit Timing 2.0A - Considers 29 bit ID as an error 2.0B Passive - Ignores 29 bit ID messages 2.0B Active - Handles both 11 and 29 bit ID Messages
To ensure correct sampling up to the last bit, a CAN node needs to re-synchronize throughout the entire frame. This is done at the beginning of each message with the falling edge SOF and on each recessive to dominant edge. One CAN bit time is specified as four non-overlapping time segments. Each segment is constructed from an integer multiple of the Time Quantum. The Time Quantum or TQ is the smallest discrete timing resolution used by a CAN node.
Bit Construction
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Figure 45. CAN Bit Construction
CAN Frame (producer) Transmission Point (producer)
Nominal CAN Bit Time Time Quantum (producer) Segments (producer) SYNC_SEG
propagation delay
PROP_SEG
PHASE_SEG_1
PHASE_SEG_2
Segments (consumer)
SYNC_SEG
PROP_SEG
PHASE_SEG_1
PHASE_SEG_2
Sample Point
Synchronization Segment
The first segment is used to synchronize the various bus nodes. On transmission, at the start of this segment, the current bit level is output. If there is a bit state change between the previous bit and the current bit, then the bus state change is expected to occur within this segment by the receiving nodes.
Propagation Time Segment
This segment is used to compensate for signal delays across the network. This is necessary to compensate for signal propagation delays on the bus line and through the transceivers of the bus nodes.
Phase Segment 1
Phase Segment 1 is used to compensate for edge phase errors. This segment may be lengthened during resynchronization.
Sample Point
The sample point is the point of time at which the bus level is read and interpreted as the value of the respective bit. Its location is at the end of Phase Segment 1 (between the two Phase Segments). This segment is also used to compensate for edge phase errors. This segment may be shortened during resynchronization, but the length has to be at least as long as the information processing time and may not be more than the length of Phase Segment 1.
Phase Segment 2
Information Processing Time
It is the time required for the logic to determine the bit level of a sampled bit. The Information processing Time begins at the sample point, is measured in TQ and is fixed at 2 TQ for the Atmel CAN. Since Phase Segment 2 also begins at the sample point and is the last segment in the bit time, Phase Segment 2 minimum shall not be less than the Information processing Time.
Bit Lengthening
As a result of resynchronization, Phase Segment 1 may be lengthened or Phase Segment 2 may be shortened to compensate for oscillator tolerances. If, for example, the transmitter oscillator is slower than the receiver oscillator, the next falling edge used for resynchronization may be delayed. So Phase Segment 1 is lengthened in order to adjust the sample point and the end of the bit time.
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Bit Shortening If, on the other hand, the transmitter oscillator is faster than the receiver one, the next falling edge used for resynchronization may be too early. So Phase Segment 2 in bit N is shortened in order to adjust the sample point for bit N+1 and the end of the bit time The limit to the amount of lengthening or shortening of the Phase Segments is set by the Resynchronization Jump Width. This segment may not be longer than Phase Segment 2. Programming the Sample Point Programming of the sample point allows "tuning" of the characteristics to suit the bus. Early sampling allows more Time Quanta in the Phase Segment 2 so the Synchronization Jump Width can be programmed to its maximum. This maximum capacity to shorten or lengthen the bit time decreases the sensitivity to node oscillator tolerances, so that lower cost oscillators such as ceramic resonators may be used. Late sampling allows more Time Quanta in the Propagation Time Segment which allows a poorer bus topology and maximum bus length. Arbitration Figure 46. Bus Arbitration
Arbitration lost
node A TXCAN node B TXCAN
Synchronization Jump Width
Node A loses the bus Node B wins the bus
CAN bus
SOF ID10 ID9 ID8 ID7 ID6 ID5 ID4 ID3 ID2 ID1 ID0 RTR IDE
---------
The CAN protocol handles bus accesses according to the concept called "Carrier Sense Multiple Access with Arbitration on Message Priority". During transmission, arbitration on the CAN bus can be lost to a competing device with a higher priority CAN Identifier. This arbitration concept avoids collisions of messages whose transmission was started by more than one node simultaneously and makes sure the most important message is sent first without time loss. The bus access conflict is resolved during the arbitration field mostly over the identifier value. If a data frame and a remote frame with the same identifier are initiated at the same time, the data frame prevails over the remote frame (c.f. RTR bit). Errors Error at Message Level The CAN protocol signals any errors immediately as they occur. Three error detection mechanisms are implemented at the message level and two at the bit level: * Cyclic Redundancy Check (CRC) The CRC safeguards the information in the frame by adding redundant check bits at the transmission end. At the receiver these bits are re-computed and tested against the received bits. If they do not agree there has been a CRC error. Frame Check This mechanism verifies the structure of the transmitted frame by checking the bit
*
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fields against the fixed format and the frame size. Errors detected by frame checks are designated "format errors". * ACK Errors As already mentioned frames received are acknowledged by all receivers through positive acknowledgement. If no acknowledgement is received by the transmitter of the message an ACK error is indicated. Monitoring The ability of the transmitter to detect errors is based on the monitoring of bus signals. Each node which transmits also observes the bus level and thus detects differences between the bit sent and the bit received. This permits reliable detection of global errors and errors local to the transmitter. Bit Stuffing The coding of the individual bits is tested at bit level. The bit representation used by CAN is "Non Return to Zero (NRZ)" coding, which guarantees maximum efficiency in bit coding. The synchronization edges are generated by means of bit stuffing.
Error at Bit Level
*
*
Error Signalling
If one or more errors are discovered by at least one node using the above mechanisms, the current transmission is aborted by sending an "error flag". This prevents other nodes accepting the message and thus ensures the consistency of data throughout the network. After transmission of an erroneous message that has been aborted, the sender automatically re-attempts transmission.
CAN Controller Description
The CAN Controller accesses are made through SFR. Several operations are possible by SFR: * * arithmetic and logic operations, transfers and program control (SFR is accessible by direct addressing). 15 independent message objects are implemented, a pagination system manages their accesses.
Any message object can be programmed in a reception buffer block (even non-consecutive buffers). For the reception of defined messages one or several receiver message objects can be masked without participating in the buffer feature. An IT is generated when the buffer is full. The frames following the buffer-full interrupt will not be taken into account until at least one of the buffer message objects is re-enabled in reception. Higher priority of a message object for reception or transmission is given to the lower message object number. The programmable 16-bit Timer (CANTIMER) is used to stamp each received and sent message in the CANSTMP register. This timer starts counting as soon as the CAN controller is enabled by the ENA bit in the CANGCON register. The Time Trigger Communication (TTC) protocol is supported by the AT89C51CC03.
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Figure 47. CAN Controller Block Diagram Bit Stuffing /Destuffing TxDC RxDC Bit Timing Logic Error Counter Rec/Tec Cyclic Redundancy Check Receive Transmit
Page Register
DPR(Mailbox + Registers)
Priority Encoder
C-Core Interface
Interface Bus
Core Control
CAN Controller Mailbox and Registers Organization
The pagination allows management of the 321 registers including 300(15x20) Bytes of mailbox via 34 SFR's. All actions on the message object window SFRs apply to the corresponding message object registers pointed by the message object number find in the Page message object register (CANPAGE) as illustrate in Figure 48.
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Figure 48. CAN Controller Memory Organization
SFR's
General Control General Status General Interrupt Bit Timing - 1 Bit Timing - 2 Bit Timing - 3 Enable message object - 1 Enable message object - 2 Enable Interrupt Enable Interrupt message object - 1 Enable Interrupt message object - 2 Status Interrupt message object - 1 Status Interrupt message object - 2
On-chip CAN Controller registers
Timer Control
CANTimer High
CANTimer Low
TimTTC High TimTTC Low TEC counter
REC counter
Page message object
(message object number) (Data offset) 15 message objects
message object 14 - Status message object 14 - Control and DLC Ch.14 - Message Data - byte 0
message object 0 - Status message object 0 - Control and DLC message object Status message object Control and DLC Message Data ID Tag - 1 ID Tag - 2 ID Tag - 3 ID Tag - 4 ID Mask - 1 ID Mask - 2 ID Mask - 3 ID Mask - 4 TimStmp High TimStmp Low
8 Bytes
Ch.0 - Message Data - byte 0
Ch.14 - ID Tag - 1 Ch.14 - ID Tag - 2 Ch.14 - ID Tag - 3 Ch.14 - ID Tag - 4 Ch.14 - ID Mask - 1 Ch.14 - ID Mask - 2 Ch.14 - ID Mask - 3 Ch.14 - ID Mask - 4 Ch.14 TimStmp High Ch.14 TimStmp Low
Ch.0 - ID Tag - 1 Ch.0 - ID Tag - 2 Ch.0 - ID Tag - 3 Ch.0 - ID Tag - 4 Ch.0 - ID Mask- 1 Ch.0 - ID Mask- 2 Ch.0 - ID Mask- 3 Ch.0 - ID Mask - 4 Ch.0 TimStmp High Ch.0 TimStmp Low
message object Window SFRs
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Working on Message Objects The Page message object register (CANPAGE) is used to select one of the 15 message objects. Then, message object Control (CANCONCH) and message object Status (CANSTCH) are available for this selected message object number in the corresponding SFRs. A single register (CANMSG) is used for the message. The mailbox pointer is managed by the Page message object register with an auto-incrementation at the end of each access. The range of this counter is 8. Note that the maibox is a pure RAM, dedicated to one message object, without overlap. In most cases, it is not necessary to transfer the received message into the standard memory. The message to be transmitted can be built directly in the maibox. Most calculations or tests can be executed in the mailbox area which provide quicker access. In order to enable the CAN Controller correctly the following registers have to be initialized: * * * General Control (CANGCON), Bit Timing (CANBT 1, 2 and 3), And for each page of 15 message objects - - message object Control (CANCONCH), message object Status (CANSTCH).
CAN Controller Management
During operation, the CAN Enable message object registers 1 and 2 (CANEN 1 and 2) gives a fast overview of the message objects availability. The CAN messages can be handled by interrupt or polling modes. A message object can be configured as follows: * * * * Transmit message object, Receive message object, Receive buffer message object. Disable
This configuration is made in the CONCH1:2 field of the CANCONCH register (see Table 46). When a message object is configured, the corresponding ENCH bit of CANEN 1 and 2 register is set. Table 46. Configuration for CONCH1:2
CONCH 1 0 0 1 1 CONCH 2 0 1 0 1 Type of Message Object Disable Transmitter Receiver Receiver buffer
When a Transmitter or Receiver action of a message object is completed, the corresponding ENCH bit of the CANEN 1 and 2 register is cleared. In order to re-enable the message object, it is necessary to re-write the configuration in CANCONCH register. Non-consecutive message objects can be used for all three types of message objects (Transmitter, Receiver and Receiver buffer),
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Buffer Mode
Any message object can be used to define one buffer, including non-consecutive message objects, and with no limitation in number of message objects used up to 15. Each message object of the buffer must be initialized CONCH2 = 1 and CONCH1 = 1; Figure 49. Buffer mode message object 14 message object 13 message object 12 message object 11 message object 10 message object 9 message object 8 message object 7 message object 6 message object 5 message object 4 message object 3 message object 2 message object 1 message object 0
Block buffer buffer 7 buffer 6 buffer 5 buffer 4 buffer 3 buffer 2 buffer 1 buffer 0
The same acceptance filter must be defined for each message objects of the buffer. When there is no mask on the identifier or the IDE, all messages are accepted. A received frame will always be stored in the lowest free message object. When the flag Rxok is set on one of the buffer message objects, this message object can then be read by the application. This flag must then be cleared by the software and the message object re-enabled in buffer reception in order to free the message object. The OVRBUF flag in the CANGIT register is set when the buffer is full. This flag can generate an interrupt. The frames following the buffer-full interrupt will not stored and no status will be overwritten in the CANSTCH registers involved in the buffer until at least one of the buffer message objects is re-enabled in reception. This flag must be cleared by the software in order to acknowledge the interrupt.
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IT CAN Management
The different interrupts are: * * * * * Transmission interrupt, Reception interrupt, Interrupt on error (bit error, stuff error, crc error, form error, acknowledge error), Interrupt when Buffer receive is full, Interrupt on overrun of CAN Timer.
Figure 50. CAN Controller Interrupt Structure
CANGIE.5 CANGIE.4 CANGIE.3
ENRX
ENTX ENERCH
RXOK i
CANSTCH.5
CANSIT1/2
TXOK i
CANSTCH.6
SIT i
CANIE1/2
BERR i
CANSTCH.4
EICH i
i=0 SIT i
SERR i
CANSTCH.3
CERR i
CANSTCH.2
i=14
FERR i
CANSTCH.1
CANGIE.2
AERR i
CANSTCH.0
ENBUF
IEN1.0
ECAN CANIT
CANGIT.7
OVRBUF
CANGIT.4 CANGIE.1
SERG
CANGIT.3
ENERG
CERG
CANGIT.2
FERG
CANGIT.1 IEN1.2
AERG
CANGIT.0
ETIM
OVRTIM
CANGIT.5
OVRIT
To enable a transmission interrupt: * * * * * * Enable General CAN IT in the interrupt system register, Enable interrupt by message object, EICHi, Enable transmission interrupt, ENTX. Enable General CAN IT in the interrupt system register, Enable interrupt by message object, EICHi, Enable reception interrupt, ENRX.
To enable a reception interrupt:
To enable an interrupt on message object error:
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* * * * * * * *
Enable General CAN IT in the interrupt system register, Enable interrupt by message object, EICHi, Enable interrupt on error, ENERCH. Enable General CAN IT in the interrupt system register, Enable interrupt on error, ENERG. Enable General CAN IT in the interrupt system register, Enable interrupt on Buffer full, ENBUF. Enable Overrun IT in the interrupt system register.
To enable an interrupt on general error:
To enable an interrupt on Buffer-full condition:
To enable an interrupt when Timer overruns: When an interrupt occurs, the corresponding message object bit is set in the SIT register. To acknowledge an interrupt, the corresponding CANSTCH bits (RXOK, TXOK,...) or CANGIT bits (OVRTIM, OVRBUF,...), must be cleared by the software application. When the CAN node is in transmission and detects a Form Error in its frame, a bit Error will also be raised. Consequently, two consecutive interrupts can occur, both due to the same error. When a message object error occurs and is set in CANSTCH register, no general error are set in CANGIE register.
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Bit Timing and Baud Rate
FSM's (Finite State Machine) of the CAN channel need to be synchronous to the time quantum. So, the input clock for bit timing is the clock used into CAN channel FSM's. Field and segment abbreviations: * * * * * * * * BRP: Baud Rate Prescaler. TQ: Time Quantum (output of Baud Rate Prescaler). SYNS: SYNchronization Segment is 1 TQ long. PRS: PRopagation time Segment is programmable to be 1, 2, ..., 8 TQ long. PHS1: PHase Segment 1 is programmable to be 1, 2, ..., 8 TQ long. PHS2: PHase Segment 2 is programmable to be superior or equal to the INFORMATION PROCESSING TIME and inferior or equal to TPSH1. INFORMATION PROCESSING TIME is 2 TQ. SJW: (Re) Synchronization Jump Width is programmable to be minimum of PHS1 and 4.
The total number of TQ in a bit time has to be programmed at least from 8 to 25.
Figure 51. Sample And Transmission Point
Bit Timing FCAN CLOCK System clock Tscl Time Quantum PRS 3-bit length PHS1 3-bit length PHS2 3-bit length SJW 2-bit length Sample point Transmission point
Prescaler BRP
The baud rate selection is made by Tbit calculation: Tbit = Tsyns + Tprs + Tphs1 + Tphs2 1. Tsyns = Tscl = (BRP[5..0]+ 1)/Fcan = 1TQ. 2. Tprs = (1 to 8) * Tscl = (PRS[2..0]+ 1) * Tscl 3. Tphs1 = (1 to 8) * Tscl = (PHS1[2..0]+ 1) * Tscl 4. Tphs2 = (1 to 8) * Tscl = (PHS2[2..0]+ 1) * Tscl Tphs2 = Max of (Tphs1 and 2TQ) 5. Tsjw = (1 to 4) * Tscl = (SJW[1..0]+ 1) * Tscl The total number of Tscl (Time Quanta) in a bit time must be comprised between 8 to 25.
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Figure 52. General Structure of a Bit Period
1/ Fcan oscillator Tscl system clock Bit Rate Prescaler
data Tsyns (*) (1) Phase error 0 (2) Phase error 0 (3) Phase error > 0 (4) Phase error < 0
one nominal bit
Tprs Tphs1 (1) Tphs1 + Tsjw (3) Tphs2 - Tsjw (4) Tbit (*) Synchronization Segment: SYNS Tsyns = 1xTscl (fixed) Sample Point Transmission Point Tphs2 (2)
Tbit calculation: Tbit = Tsyns + Tprs + Tphs1 + Tphs2
example of bit timing determination for CAN baudrate of 500kbit/s: Fosc = 12 MHz in X1 mode => FCAN = 6 MHz Verify that the CAN baud rate you want is an integer division of FCAN clock. FCAN/CAN baudrate = 6 MHz/500 kHz = 12 The time quanta TQ must be comprised between 8 and 25: TQ = 12 and BRP = 0 Define the various timing parameters: Tbit = Tsyns + Tprs + Tphs1 + Tphs2 = 12TQ Tsyns = 1TQ and Tsjw =1TQ => SJW = 0 If we chose a sample point at 66.6% => Tphs2 = 4TQ => PHS2 = 3 Tbit = 12 = 4 + 1 + Tphs1 + Tprs, let us choose Tprs = 3 Tphs1 = 4 PHS1 = 3 and PRS = 2 BRP = 0 so CANBT1 = 00h SJW = 0 and PRS = 2 so CANBT2 = 04h PHS2 = 3 and PHS1 = 3 so CANBT3 = 36h
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Fault Confinement
With respect to fault confinement, a unit may be in one of the three following status: * * * error active error passive bus off
An error active unit takes part in bus communication and can send an active error frame when the CAN macro detects an error. An error passive unit cannot send an active error frame. It takes part in bus communication, but when an error is detected, a passive error frame is sent. Also, after a transmission, an error passive unit will wait before initiating further transmission. A bus off unit is not allowed to have any influence on the bus. For fault confinement, two error counters (TEC and REC) are implemented. See CAN Specification for details on Fault confinement. Figure 53. Line Error Mode ERRP = 0 BOFF = 0
Init. Error Active TEC<127 and REC<127
TEC: Transmit Error Counter REC: Receive Error Counter
TEC>127 or REC>127
128 occurrences of 11 consecutive recessive bit Bus Off
Error Passive ERRP = 0 BOFF = 0 TEC>255
ERRP = 0 BOFF = 1
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Acceptance Filter
Upon a reception hit (i.e., a good comparison between the ID+RTR+RB+IDE received and an ID+RTR+RB+IDE specified while taking the comparison mask into account) the ID+RTR+RB+IDE received are written over the ID TAG Registers. ID => IDT0-29 RTR => RTRTAG RB => RB0-1TAG IDE => IDE in CANCONCH register Figure 54. Acceptance filter block diagram
RxDC Rx Shift Register (internal)
ID and RB 13/32 RTR IDE
=
13/32 Write Enable 13/32 1
13/32 Hit (Ch i) 13/32
ID TAG Registers (Ch i) and CanConch
ID and RB RTR IDE
ID MSK Registers (Ch i)
ID and RB RTR IDE
example: To accept only ID = 318h in part A. ID MSK = 111 1111 1111 b ID TAG = 011 0001 1000 b
CAN SFRs
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Data and Remote Frame
Description of the different steps for: * Data Frame
Node A
H RP L TX V RXOK O K RT R EN C
Node B
H RP LV TX RXOK O K RT R EN C
message object in transmission message object disabled
01 uu 00 uc
x 00 u uu x 10 u cu
DA
TA FR A
01 uu
ME
x 00 u uu x 01 u uc
message object in reception
00 uc
message object disabled
*
Remote Frame, With Automatic Reply,
message object in transmission message object in reception by CAN controller message object disabled
RT R EN CH RP L TX V RXOK O K
RT R EN CH RP L TX V O RX K O K
RE MO TE FR
11 uu 01 cu 00 uc
x 00 u uu x 10 u cu x 01 u uc
11 uu
AM E
1 00 u uu 0 00 c uu 0 10 c cu
message object in reception
ME FRAe) ATAediat Dm (im
01 cu 00 uc
message object in transmission by CAN controller message object disabled
*
Remote Frame
RT R EN CH RP L TX V O RX K O K
RT R EN CH RP L TX V RXOK O K
RE MO TE F
message object in transmission message object disabled
11 uu 01 cu
x 00 u uu x 10 u cu
11 uu
RA ME
0 00 u uu 0 01 u uc
message object in reception
10 uc
message object disabled
message object in reception by user
00 cc
x 01 u uc
E AM FR ) TA rred DA e f e (d
01 uu 00 uc
x 00 u uu x 10 u cu
message object in transmission by user
message object disabled
i u : modified by user
i c : modified by CAN
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Time Trigger Communication (TTC) and Message Stamping
The AT89C51CC03 has a programmable 16-bit Timer (CANTIMH and CANTIML) for message stamp and TTC. This CAN Timer starts after the CAN controller is enabled by the ENA bit in the CANGCON register. Two modes in the timer are implemented: * Time Trigger Communication: - Capture of this timer value in the CANTTCH and CANTTCL registers on Start Of Frame (SOF) or End Of Frame (EOF), depending on the SYNCTTC bit in the CANGCON register, when the network is configured in TTC by the TTC bit in the CANGCON register.
In this mode, CAN only sends the frame once, even if an error occurs.
Note:
*
Message Stamping - - - - Capture of this timer value in the CANSTMPH and CANSTMPL registers of the message object which received or sent the frame. All messages can be stamps. The stamping of a received frame occurs when the RxOk flag is set. The stamping of a sent frame occurs when the TxOk flag is set.
The CAN Timer works in a roll-over from FFFFh to 0000h which serves as a time base. When the timer roll-over from FFFFh to 0000h, an interrupt is generated if the ETIM bit in the interrupt enable register IEN1 is set. Figure 55. Block Diagram of CAN Timer
When 0xFFFF to 0x0000
OVRTIM
CANGIT.5
Fcan CLOCK
/6
CANTCON
CANGCON.1
ENA
CANGCON.5 CANGCON.4 TTC SYNCTTC
CANTIMH and CANTIML TXOK i
CANSTCH.4
SOF on CAN frame EOF on CAN frame
RXOK i
CANSTCH.5
CANSTMPH and CANSTMPL CANTTCH and CANTTCL
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CAN Autobaud and Listening Mode
To activate the Autobaud feature, the AUTOBAUD bit in the CANGCON register must be set. In this mode, the CAN controller is only listening to the line without acknowledging the received messages. It cannot send any message. The error flags are updated. The bit timing can be adjusted until no error occurs (good configuration find). In this mode, the error counters are frozen. To go back to the standard mode, the AUTOBAUD bit must be cleared. Figure 56. Autobaud Mode
TxDC' TxDC
AUTOBAUD CANGCON.3
RxDC
RxDC'
1 0
Routines Examples
1. Init of CAN macro
// Reset the CAN macro CANGCON = 01h; // Disable CAN interrupts ECAN = 0; ETIM = 0; // Init the Mailbox for num_page =0; num_page <15; num_page++ { CANPAGE = num_channel << 4; CANCONCH = 00h CANSTCH = 00h; CANIDT1 = 00h; CANIDT2 = 00h; CANIDT3 = 00h; CANIDT4 = 00h; CANIDM1 = 00h; CANIDM2 = 00h; CANIDM3 = 00h; CANIDM4 = 00h; for num_data =0; num_data <8; num_data++) { CANMSG = 00h; } } // Configure the bit timing CANBT1 = xxh CANBT2 = xxh CANBT3 = xxh
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// Enable the CAN macro CANGCON = 02h
2. Configure message object 3 in reception to receive only standard (11-bit identifier) message 100h
// Select the message object 3 CANPAGE = 30h // Enable the interrupt on this message object CANIE2 = 08h // Clear the status and control register CANSTCH = 00h CANCONCH = 00h // Init the acceptance filter to accept only message 100h in standard mode CANIDT1 = 20h CANIDT2 = 00h CANIDT3 = 00h CANIDT4 = 00h CANIDM1 = FFh CANIDM2 = FFh CANIDM3 = FFh CANIDM4 = FFh // Enable channel in reception CANCONCH = 88h // enable reception
Note:
To enable the CAN interrupt in reception:
EA = 1 ECAN = 1 CANGIE = 20h
3. Send a message on the message object 12
// Select the message object 12 CANPAGE = C0h // Enable the interrupt on this message object CANIE1 = 01h // Clear the Status register CANSTCH = 00h; // load the identifier to send (ex: 555h) CANIDT1 = AAh; CANIDT2 = A0h; // load data to send CANMSG = 00h CANMSG = 01h CANMSG = 02h CANMSG = 03h CANMSG = 04h CANMSG = 05h CANMSG = 06h CANMSG = 07h // configure the control register CANCONCH = 18h
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4. Interrupt routine
// Save the current CANPAGE // Find the first message object which generate an interrupt in CANSIT1 and CANSIT2 // Select the corresponding message object // Analyse the CANSTCH register to identify which kind of interrupt is generated // Manage the interrupt // Clear the status register CANSTCH = 00h; // if it is not a channel interrupt but a general interrupt // Manage the general interrupt and clear CANGIT register // restore the old CANPAGE
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CAN SFR's
Table 47. CAN SFR's With Reset Values
0/8(1) F8h F0h E8h E0h D8h IPL1 xxxx x000 B 0000 0000 IEN1 xxxx x000 ACC 0000 0000 CCON 00xx xx00 PSW 0000 0000 T2CON 0000 0000 P4 xxxx xx11 IPL0 x000 0000 P3 1111 1111 IEN0 0000 0000 P2 1111 1111 SCON 0000 0000 P1 1111 1111 TCON 0000 0000 P0 1111 1111 0/8
(1)
1/9 CH 0000 0000
2/A CCAP0H 0000 0000 ADCLK xx00 x000
3/B CCAP1H 0000 0000 ADCON 0000 0000 CCAP1L 0000 0000
4/C CCAP2H 0000 0000 ADDL xxxx xx00 CCAP2L 0000 0000
5/D CCAP3H 0000 0000 ADDH 0000 0000 CCAP3L 0000 0000
6/E CCAP4H 0000 0000 ADCF 0000 0000 CCAP4L 0000 0000
7/F FFh IPH1 xxxx x000 F7h EFh E7h
CL 0000 0000
CCAP0L 0000 0000
CMOD 00xx x000 FCON 0000 0000 T2MOD xxxx xx00 CANGIE 0000 0000 SADEN 0000 0000 CANPAGE 0000 0000 SADDR 0000 0000 CANTCON 0000 0000 SBUF 0000 0000
CCAPM0 x000 0000 EECON xxxx xx00 RCAP2L 0000 0000 CANIE1 xx00 0000 CANSIT1 0x00 0000 CANSTCH xxxx xxxx CANGSTA 0000 0000 AUXR1 xxxx 00x0
CCAPM1 x000 0000 FSTA xxxx xx00 RCAP2H 0000 0000 CANIE2 0000 0000 CANSIT2 0000 0000 CANCONCH xxxx xxxx CANGCON 0000 x000 CANMSG xxxx xxxx CANGIT 0x00 0000
CCAPM2 x000 0000 SPCON 0001 0100 TL2 0000 0000 CANIDM1 xxxx xxxx CANIDT1 xxxx xxxx CANBT1 xxxx xxxx CANTIML 0000 0000 CANTTCL 0000 0000 CANTEC 0000 0000
CCAPM3 x000 0000 SPSCR 0000 0000 TH2 0000 0000 CANIDM2 xxxx xxxx CANIDT2 xxxx xxxx CANBT2 xxxx xxxx CANTIMH 0000 0000 CANTTCH 0000 0000 CANREC 0000 0000
CCAPM4 x000 0000 SPDAT xxxx xxxx CANEN1 xx00 0000 CANIDM3 xxxx xxxx CANIDT3 xxxx xxxx CANBT3 xxxx xxxx CANSTMPL 0000 0000 WDTRST 1111 1111 CANEN2 0000 0000 CANIDM4 xxxx xxxx CANIDT4 xxxx xxxx IPH0 x000 0000 CANSTMPH 0000 0000 WDTPRG xxxx x000 CKCON1 xxxx xxx0
DFh
D0h C8h C0h B8h B0h A8h A0h
D7h CFh C7h BFh B7h AFh A7h
98h 90h 88h 80h
9Fh 97h
TMOD 0000 0000 SP 0000 0111 1/9
TL0 0000 0000 DPL 0000 0000 2/A
TL1 0000 0000 DPH 0000 0000 3/B
TH0 0000 0000
TH1 0000 0000
AUXR X001 0100
CKCON 0000 0000 PCON 0000 0000
8Fh 87h
4/C
5/D
6/E
7/F
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Registers
Table 48. CANGCON Register CANGCON (S:ABh) CAN General Control Register
7 ABRQ Bit Number 6 OVRQ 5 TTC 4 SYNCTTC 3 AUTOBAUD 2 TEST 1 ENA 0 GRES
Bit Mnemonic Description Abort Request Not an auto-resetable bit. A reset of the ENCH bit (message object control and DLC register) is done for each message object. The pending transmission communications are immediately aborted but the on-going communication will be terminated normally, setting the appropriate status flags, TXOK or RXOK. Overload frame request (initiator) Auto-resetable bit. Set to send an overload frame after the next received message. Cleared by the hardware at the beginning of transmission of the overload frame. Network in Timer Trigger Communication set to select node in TTC. clear to disable TTC features. Synchronization of TTC When this bit is set the TTC timer is caught on the last bit of the End Of Frame. When this bit is clear the TTC timer is caught on the Start Of Frame. This bit is only used in the TTC mode. AUTOBAUD Set to activate listening mode. Clear to disable listening mode
7
ABRQ
6
OVRQ
5
TTC
4
SYNCTTC
3
AUTOBAUD
2
TEST
Test mode. The test mode is intended for factory testing and not for customer use. Enable/Standby CAN Controller When this bit is set, it enables the CAN controller and its input clock. When this bit is clear, the on-going communication is terminated normally and the CAN controller state of the machine is frozen (the ENCH bit of each message object does not change). In the standby mode, the transmitter constantly provides a recessive level; the receiver is not activated and the input clock is stopped in the CAN controller. During the disable mode, the registers and the mailbox remain accessible. Note that two clock periods are needed to start the CAN controller state of the machine. General Reset (software reset) Auto-resetable bit. This reset command is `ORed' with the hardware reset in order to reset the controller. After a reset, the controller is disabled.
1
ENA/STB
0
GRES
Reset Value = 0000 0x00b
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Table 49. CANGSTA Register CANGSTA (S:AAh) CAN General Status Register
7 Bit Number 7 6 OVFG 5 4 TBSY 3 RBSY 2 ENFG 1 BOFF 0 ERRP
Bit Mnemonic Description Reserved The values read from this bit is indeterminate. Do not set this bit. Overload Frame Flag(1)
6
OVFG
This status bit is set by the hardware as long as the produced overload frame is sent. This flag does not generate an interrupt Reserved The values read from this bit is indeterminate. Do not set this bit. Transmitter Busy(1)
5
-
4
TBSY
This status bit is set by the hardware as long as the CAN transmitter generates a frame (remote, data, overload or error frame) or an ack field. This bit is also active during an InterFrame Spacing if a frame must be sent. This flag does not generate an interrupt. Receiver Busy(1)
3
RBSY
This status bit is set by the hardware as long as the CAN receiver acquires or monitors a frame. This flag does not generate an interrupt. Enable On-chip CAN Controller Flag(1)
2
ENFG
Because an enable/disable command is not effective immediately, this status bit gives the true state of a chosen mode. This flag does not generate an interrupt. Bus Off Mode(1) see Figure 53 Error Passive Mode(1) see Figure 53
1
BOFF
0
ERRP
Note:
1. These fields are Read Only.
Reset Value = x0x0 0000b
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Table 50. CANGIT Register CANGIT (S:9Bh) CAN General Interrupt
7 CANIT Bit Number 6 5 OVRTIM 4 OVRBUF 3 SERG 2 CERG 1 FERG 0 AERG
Bit Mnemonic Description General Interrupt Flag(1)
7
CANIT
This status bit is the image of all the CAN controller interrupts sent to the interrupt controller. It can be used in the case of the polling method. Reserved The values read from this bit is indeterminate. Do not set this bit. Overrun CAN Timer This status bit is set when the CAN timer switches 0xFFFF to 0x0000. If the bit ETIM in the IE1 register is set, an interrupt is generated. Clear this bit in order to reset the interrupt. Overrun BUFFER 0 - no interrupt. 1 - IT turned on This bit is set when the buffer is full. Bit resetable by user. see Figure 50. Stuff Error General Detection of more than five consecutive bits with the same polarity. This flag can generate an interrupt. resetable by user. CRC Error General The receiver performs a CRC check on each destuffed received message from the start of frame up to the data field. If this checking does not match with the destuffed CRC field, a CRC error is set. This flag can generate an interrupt. resetable by user. Form Error General The form error results from one or more violations of the fixed form in the following bit fields: CRC delimiter acknowledgment delimiter end_of_frame This flag can generate an interrupt. resetable by user. Acknowledgment Error General No detection of the dominant bit in the acknowledge slot. This flag can generate an interrupt. resetable by user.
6
-
5
OVRTIM
4
OVRBUF
3
SERG
2
CERG
1
FERG
0
AERG
Note:
1. These fields are Read Only.
Reset Value = 0x00 0000b
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Table 51. CANTEC Register CANTEC (S:9Ch Read Only) CAN Transmit Error Counter
7 TEC7 Bit Number 7-0 6 TEC6 5 TEC5 4 TEC4 3 TEC3 2 TEC2 1 TEC1 0 TEC0
Bit Mnemonic Description TEC7:0 Transmit Error Counter see Figure 53
Reset Value = 00h Table 52. CANREC Register CANREC (S:9Dh Read Only) CAN Reception Error Counter
7 REC7 Bit Number 7-0 6 REC6 5 REC5 4 REC4 3 REC3 2 REC2 1 REC1 0 REC0
Bit Mnemonic Description REC7:0 Reception Error Counter see Figure 53
Reset Value = 00h
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Table 53. CANGIE Register CANGIE (S:C1h) CAN General Interrupt Enable
7 Bit Number 7-6 6 5 ENRX 4 ENTX 3 ENERCH 2 ENBUF 1 ENERG 0 -
Bit Mnemonic Description Reserved The values read from these bits are indeterminate. Do not set these bits. Enable Receive Interrupt 0 - Disable 1 - Enable Enable Transmit Interrupt 0 - Disable 1 - Enable Enable Message Object Error Interrupt 0 - Disable 1 - Enable Enable BUF Interrupt 0 - Disable 1 - Enable Enable General Error Interrupt 0 - Disable 1 - Enable Reserved The value read from this bit is indeterminate. Do not set this bit.
5
ENRX
4
ENTX
3
ENERCH
2
ENBUF
1
ENERG
0
-
Note:
See Figure 50
Reset Value = xx00 000xb
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Table 54. CANEN1 Register CANEN1 (S:CEh Read Only) CAN Enable Message Object Registers 1
7 Bit Number 7 6 ENCH14 5 ENCH13 4 ENCH12 3 ENCH11 2 ENCH10 1 ENCH9 0 ENCH8
Bit Mnemonic Description Reserved The values read from this bit is indeterminate. Do not set this bit. Enable Message Object These bits provide the availability of the MOb. It is set to one when the MOb is enabled. Once TXOK or RXOK is set to one (TXOK for automatic reply), the corresponding ENMOB is reset. ENMOB is also set to zero configuring the MOb in disabled mode, applying abortion or standby mode. 0 - message object disabled: MOb available for a new transmission or reception. 1 - message object enabled: MOb in use. This bit is resetable by re-writing the CANCONCH of the corresponding message object.
6-0
ENCH14:8
Reset Value = x000 0000b Table 55. CANEN2 Register CANEN2 (S:CFh Read Only) CAN Enable Message Object Registers 2
7 ENCH7 Bit Number 6 ENCH6 5 ENCH5 4 ENCH4 3 ENCH3 2 ENCH2 1 ENCH1 0 ENCH0
Bit Mnemonic Description Enable Message Object These bits provide the availability of the MOb. It is set to one when the MOb is enabled. Once TXOK or RXOK is set to one (TXOK for automatic reply), the corresponding ENMOB is reset. ENMOB is also set to zero configuring the MOb in disabled mode, applying abortion or standby mode. 0 - message object disabled: MOb available for a new transmission or reception. 1 - message object enabled: MOb in use. This bit is resetable by re-writing the CANCONCH of the corresponding message object.
7-0
ENCH7:0
Reset Value = 0000 0000b
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Table 56. CANSIT1 Register CANSIT1 (S:BAh) CAN Status Interrupt Message Object Registers 1
7 Bit Number 7 6 SIT14 5 SIT13 4 SIT12 3 SIT11 2 SIT10 1 SIT9 0 SIT8
Bit Mnemonic Description Reserved The values read from this bit is indeterminate. Do not set this bit. Status of Interrupt by Message Object (1)
6-0
SIT14:8
0 - no interrupt. 1 - IT turned on. Reset when interrupt condition is cleared by user. SIT14:8 = 0b 0000 1001 -> IT's on message objects 11 and 8. see Figure 50.
Note:
1. This field is Read Only
Reset Value = x000 0000b Table 57. CANSIT2 Register CANSIT2 (S:BBh Read Only) CAN Status Interrupt Message Object Registers 2
7 SIT7 Bit Number 6 SIT6 5 SIT5 4 SIT4 3 SIT3 2 SIT2 1 SIT1 0 SIT0
Bit Mnemonic Description Status of Interrupt by Message Object 0 - no interrupt. 1 - IT turned on. Reset when interrupt condition is cleared by user. SIT7:0 = 0b 0000 1001 -> IT's on message objects 3 and 0 see Figure 50.
7-0
SIT7:0
Reset Value = 0000 0000b
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Table 58. CANIE1 Register CANIE1 (S:C2h) CAN Enable Interrupt Message Object Registers 1
7 Bit Number 7 6 IECH14 5 IECH13 4 IECH12 3 IECH11 2 IECH10 1 IECH9 0 IECH8
Bit Mnemonic Description Reserved The values read from this bit is indeterminate. Do not set this bit. Enable interrupt by Message Object 0 - disable IT. 1 - enable IT. IECH14:8 = 0b 0000 1100 -> Enable IT's of message objects 11 and 10. see Figure 50.
6-0
IECH14:8
Reset Value = x000 0000b Table 59. CANIE2 Register CANIE2 (S:C3h) CAN Enable Interrupt Message Object Registers 2
7 IECH 7 Bit Number 6 IECH 6 5 IECH 5 4 IECH 4 3 IECH 3 2 IECH 2 1 IECH 1 0 IECH 0
Bit Mnemonic Description Enable interrupt by Message Object 0 - disable IT. 1 - enable IT. IECH7:0 = 0b 0000 1100 -> Enable IT's of message objects 3 and 2.
7-0
IECH7:0
Reset Value = 0000 0000b
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Table 60. CANBT1 Register CANBT1 (S:B4h) CAN Bit Timing Registers 1
7 Bit Number 7 6 BRP 5 5 BRP 4 4 BRP 3 3 BRP 2 2 BRP 1 1 BRP 0 0 -
Bit Mnemonic Description Reserved The value read from this bit is indeterminate. Do not set this bit. Baud rate prescaler The period of the CAN controller system clock Tscl is programmable and determines the individual bit timing.
6-1
BRP5:0 Tscl = BRP[5..0] + 1 Fcan
0
-
Reserved The value read from this bit is indeterminate. Do not set this bit.
Note:
The CAN controller bit timing registers must be accessed only if the CAN controller is disabled with the ENA bit of the CANGCON register set to 0. See Figure 52.
No default value after reset.
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Table 61. CANBT2 Register CANBT2 (S:B5h) CAN Bit Timing Registers 2
7 Bit Number 7 6 SJW 1 5 SJW 0 4 3 PRS 2 2 PRS 1 1 PRS 0 0 -
Bit Mnemonic Description Reserved The value read from this bit is indeterminate. Do not set this bit. Re-synchronization Jump Width To compensate for phase shifts between clock oscillators of different bus controllers, the controller must re-synchronize on any relevant signal edge of the current transmission. The synchronization jump width defines the maximum number of clock cycles. A bit period may be shortened or lengthened by a re-synchronization. Tsjw = Tscl x (SJW [1..0] +1) Reserved The value read from this bit is indeterminate. Do not set this bit. Programming Time Segment This part of the bit time is used to compensate for the physical delay times within the network. It is twice the sum of the signal propagation time on the bus line, the input comparator delay and the output driver delay. Tprs = Tscl x (PRS[2..0] + 1) Reserved The value read from this bit is indeterminate. Do not set this bit.
6-5
SJW1:0
4
-
3-1
PRS2:0
0
-
Note:
The CAN controller bit timing registers must be accessed only if the CAN controller is disabled with the ENA bit of the CANGCON register set to 0. See Figure 52.
No default value after reset.
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Table 62. CANBT3 Register CANBT3 (S:B6h) CAN Bit Timing Registers 3
7 Bit Number 7 6 PHS2 2 5 PHS2 1 4 PHS2 0 3 PHS1 2 2 PHS1 1 1 PHS1 0 0 SMP
Bit Mnemonic Description Reserved The value read from this bit is indeterminate. Do not set this bit. Phase Segment 2 This phase is used to compensate for phase edge errors. This segment can be shortened by the re-synchronization jump width.
6-4
PHS2 2:0
Tphs2 = Tscl x (PHS2[2..0] + 1) Phase segment 2 is the maximum of Phase segment 1 and the Information Processing Time (= 2TQ). Phase Segment 1 This phase is used to compensate for phase edge errors. This segment can be lengthened by the re-synchronization jump width. Tphs1 = Tscl x (PHS1[2..0] + 1) Sample Type 0 - once, at the sample point. 1 - three times, the threefold sampling of the bus is the sample point and twice over a distance of a 1/2 period of the Tscl. The result corresponds to the majority decision of the three values.
3-1
PHS1 2:0
0
SMP
Note:
The CAN controller bit timing registers must be accessed only if the CAN controller is disabled with the ENA bit of the CANGCON register set to 0. See Figure 52.
No default value after reset.
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Table 63. CANPAGE Register CANPAGE (S:B1h) CAN Message Object Page Register
7 CHNB 3 Bit Number 7-4 6 CHNB 2 5 CHNB 1 4 CHNB 0 3 AINC 2 INDX2 1 INDX1 0 INDX0
Bit Mnemonic Description CHNB3:0 Selection of Message Object Number The available numbers are: 0 to 14 (see Figure 48). Auto Increment of the Index (active low) 0 - auto-increment of the index (default value). 1 - non-auto-increment of the index. Index Byte location of the data field for the defined message object (see Figure 48).
3
AINC
2-0
INDX2:0
Reset Value = 0000 0000b Table 64. CANCONCH Register CANCONCH (S:B3h) CAN Message Object Control and DLC Register
7 CONCH 1 Bit Number 6 CONCH 0 5 RPLV 4 IDE 3 DLC 3 2 DLC 2 1 DLC 1 0 DLC 0
Bit Mnemonic Description Configuration of Message Object CONCH1 CONCH0 0 0: disable 0 1: Launch transmission 1 0: Enable Reception 1 1: Enable Reception Buffer Note: The user must re-write the configuration to enable the corresponding bit in the CANEN1:2 registers. Reply Valid Used in the automatic reply mode after receiving a remote frame 0 - reply not ready. 1 - reply ready and valid. Identifier Extension 0 - CAN standard rev 2.0 A (ident = 11 bits). 1 - CAN standard rev 2.0 B (ident = 29 bits). Data Length Code Number of Bytes in the data field of the message. The range of DLC is from 0 up to 8. This value is updated when a frame is received (data or remote frame). If the expected DLC differs from the incoming DLC, a warning appears in the CANSTCH register.
7-6
CONCH1:0
5
RPLV
4
IDE
3-0
DLC3:0
No default value after reset
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Table 65. CANSTCH Register CANSTCH (S:B2h) CAN Message Object Status Register
7 DLCW Bit Number 6 TXOK 5 RXOK 4 BERR 3 SERR 2 CERR 1 FERR 0 AERR
Bit Mnemonic Description Data Length Code Warning The incoming message does not have the DLC expected. Whatever the frame type, the DLC field of the CANCONCH register is updated by the received DLC. Transmit OK The communication enabled by transmission is completed. When the controller is ready to send a frame, if two or more message objects are enabled as producers, the lower index message object (0 to 13) is supplied first. This flag can generate an interrupt. Receive OK The communication enabled by reception is completed. In the case of two or more message object reception hits, the lower index message object (0 to 13) is updated first. This flag can generate an interrupt. Bit Error (Only in Transmission) The bit value monitored is different from the bit value sent. Exceptions: the monitored recessive bit sent as a dominant bit during the arbitration field and the acknowledge slot detecting a dominant bit during the sending of an error frame. This flag can generate an interrupt. Stuff Error Detection of more than five consecutive bits with the same polarity. This flag can generate an interrupt. CRC Error The receiver performs a CRC check on each destuffed received message from the start of frame up to the data field. If this checking does not match with the destuffed CRC field, a CRC error is set. This flag can generate an interrupt. Form Error The form error results from one or more violations of the fixed form in the following bit fields: CRC delimiter acknowledgment delimiter end_of_frame This flag can generate an interrupt. Acknowledgment Error No detection of the dominant bit in the acknowledge slot. This flag can generate an interrupt.
7
DLCW
6
TXOK
5
RXOK
4
BERR
3
SERR
2
CERR
1
FERR
0
AERR
Note:
See Figure 50.
No default value after reset.
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Table 66. CANIDT1 Register for V2.0 part A CANIDT1 for V2.0 part A (S:BCh) CAN Identifier Tag Registers 1
7 IDT 10 Bit Number 7-0 6 IDT 9 5 IDT 8 4 IDT 7 3 IDT 6 2 IDT 5 1 IDT 4 0 IDT 3
Bit Mnemonic Description IDT10:3 IDentifier tag value See Figure 54.
No default value after reset. Table 67. CANIDT2 Register for V2.0 part A CANIDT2 for V2.0 part A (S:BDh) CAN Identifier Tag Registers 2
7 IDT 2 Bit Number 7-5 4-0 6 IDT 1 5 IDT 0 4 3 2 1 0 -
Bit Mnemonic Description IDT2:0 IDentifier tag value See Figure 54. Reserved The values read from these bits are indeterminate. Do not set these bits.
No default value after reset. Table 68. CANIDT3 Register for V2.0 part A CANIDT3 for V2.0 part A (S:BEh) CAN Identifier Tag Registers 3
7 Bit Number 7-0 6 5 4 3 2 1 0 -
Bit Mnemonic Description Reserved The values read from these bits are indeterminate. Do not set these bits.
No default value after reset.
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Table 69. CANIDT4 Register for V2.0 part A CANIDT4 for V2.0 part A (S:BFh) CAN Identifier Tag Registers 4
7 Bit Number 7-3 2 1 0 6 5 4 3 2 RTRTAG 1 0 RB0TAG
Bit Mnemonic Description RTRTAG RB0TAG Reserved The values read from these bits are indeterminate. Do not set these bits. Remote Transmission Request Tag Value. Reserved The values read from this bit are indeterminate. Do not set these bit. Reserved Bit 0 Tag Value.
No default value after reset. Table 70. CANIDT4 Register for V2.0 part A CANIDT1 for V2.0 part B (S:BCh) CAN Identifier Tag Registers 1
7 IDT 28 Bit Number 7-0 6 IDT 27 5 IDT 26 4 IDT 25 3 IDT 24 2 IDT 23 1 IDT 22 0 IDT 21
Bit Mnemonic Description IDT28:21 IDentifier Tag Value See Figure 54.
No default value after reset. Table 71. CANIDT2 Register for V2.0 part B CANIDT2 for V2.0 part B (S:BDh) CAN Identifier Tag Registers 2
7 IDT 20 Bit Number 7-0 6 IDT 19 5 IDT 18 4 IDT 17 3 IDT 16 2 IDT 15 1 IDT 14 0 IDT 13
Bit Mnemonic Description IDT20:13 IDentifier Tag Value See Figure 54.
No default value after reset.
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Table 72. CANIDT3 Register for V2.0 part B CANIDT3 for V2.0 part B (S:BEh) CAN Identifier Tag Registers 3
7 IDT 12 Bit Number 7-0 6 IDT 11 5 IDT 10 4 IDT 9 3 IDT 8 2 IDT 7 1 IDT 6 0 IDT 5
Bit Mnemonic Description IDT12:5 IDentifier Tag Value See Figure 54.
No default value after reset. Table 73. CANIDT4 Register for V2.0 part B CANIDT4 for V2.0 part B (S:BFh) CAN Identifier Tag Registers 4
7 IDT 4 Bit Number 7-3 2 1 0 6 IDT 3 5 IDT 2 4 IDT 1 3 IDT 0 2 RTRTAG 1 RB1TAG 0 RB0TAG
Bit Mnemonic Description IDT4:0 RTRTAG RB1TAG RB0TAG IDentifier Tag Value See Figure 54. Remote Transmission Request Tag Value Reserved bit 1 Tag Value Reserved bit 0 Tag Value
No default value after reset. Table 74. CANIDM1 Register for V2.0 part A CANIDM1 for V2.0 part A (S:C4h) CAN Identifier Mask Registers 1
7 IDMSK 10 Bit Number 6 IDMSK 9 5 IDMSK 8 4 IDMSK 7 3 IDMSK 6 2 IDMSK 5 1 IDMSK 4 0 IDMSK 3
Bit Mnemonic Description IDentifier mask value 0 - comparison true forced. 1 - bit comparison enabled. See Figure 54.
7-0
IDTMSK10:3
No default value after reset.
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Table 75. CANIDM2 Register for V2.0 part A CANIDM2 for V2.0 part A (S:C5h) CAN Identifier Mask Registers 2
7 IDMSK 2 Bit Number 6 IDMSK 1 5 IDMSK 0 4 3 2 1 0 -
Bit Mnemonic Description IDentifier Mask Value 0 - comparison true forced. 1 - bit comparison enabled. See Figure 54. Reserved The values read from these bits are indeterminate. Do not set these bits.
7-5
IDTMSK2:0
4-0
-
No default value after reset. Table 76. CANIDM3 Register for V2.0 part A CANIDM3 for V2.0 part A (S:C6h) CAN Identifier Mask Registers 3
7 Bit Number 7-0 6 5 4 3 2 1 0 -
Bit Mnemonic Description Reserved The values read from these bits are indeterminate.
No default value after reset.
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Table 77. CANIDM4 Register for V2.0 part A CANIDM4 for V2.0 part A (S:C7h) CAN Identifier Mask Registers 4
7 Bit Number 7-3 6 5 4 3 2 RTRMSK 1 0 IDEMSK
Bit Mnemonic Description Reserved The values read from these bits are indeterminate. Do not set these bits. Remote Transmission Request Mask Value 0 - comparison true forced. 1 - bit comparison enabled. Reserved The value read from this bit is indeterminate. Do not set this bit. IDentifier Extension Mask Value 0 - comparison true forced. 1 - bit comparison enabled.
2
RTRMSK
1
-
0
IDEMSK
Note:
The ID Mask is only used for reception.
No default value after reset. Table 78. CANIDM1 Register for V2.0 part B CANIDM1 for V2.0 part B (S:C4h) CAN Identifier Mask Registers 1
7 IDMSK 28 Bit Number 6 IDMSK 27 5 IDMSK 26 4 IDMSK 25 3 IDMSK 24 2 IDMSK 23 1 IDMSK 22 0 IDMSK 21
Bit Mnemonic Description IDentifier Mask Value 0 - comparison true forced. 1 - bit comparison enabled. See Figure 54.
7-0
IDMSK28:21
Note:
The ID Mask is only used for reception.
No default value after reset.
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Table 79. CANIDM2 Register for V2.0 part B CANIDM2 for V2.0 part B (S:C5h) CAN Identifier Mask Registers 2
7 IDMSK 20 Bit Number 6 IDMSK 19 5 IDMSK 18 4 IDMSK 17 3 IDMSK 16 2 IDMSK 15 1 IDMSK 14 0 IDMSK 13
Bit Mnemonic Description IDentifier Mask Value 0 - comparison true forced. 1 - bit comparison enabled. See Figure 54.
7-0
IDMSK20:13
Note:
The ID Mask is only used for reception.
No default value after reset. Table 80. CANIDM3 Register for V2.0 part B CANIDM3 for V2.0 part B (S:C6h) CAN Identifier Mask Registers 3
7 IDMSK 12 Bit Number 6 IDMSK 11 5 IDMSK 10 4 IDMSK 9 3 IDMSK 8 2 IDMSK 7 1 IDMSK 6 0 IDMSK 5
Bit Mnemonic Description IDentifier Mask Value 0 - comparison true forced. 1 - bit comparison enabled. See Figure 54.
7-0
IDMSK12:5
Note:
The ID Mask is only used for reception.
No default value after reset.
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Table 81. CANIDM4 Register for V2.0 part B CANIDM4 for V2.0 part B (S:C7h) CAN Identifier Mask Registers 4
7 IDMSK 4 Bit Number 6 IDMSK 3 5 IDMSK 2 4 IDMSK 1 3 IDMSK 0 2 RTRMSK 1 0 IDEMSK
Bit Mnemonic Description IDentifier Mask Value 0 - comparison true forced. 1 - bit comparison enabled. See Figure 54. Remote Transmission Request Mask Value 0 - comparison true forced. 1 - bit comparison enabled. Reserved The value read from this bit is indeterminate. Do not set this bit. IDentifier Extension Mask Value 0 - comparison true forced. 1 - bit comparison enabled.
7-3
IDMSK4:0
2
RTRMSK
1
-
0
IDEMSK
Note:
The ID Mask is only used for reception.
No default value after reset. Table 82. CANMSG Register CANMSG (S:A3h) CAN Message Data Register
7 MSG 7 Bit Number 6 MSG 6 5 MSG 5 4 MSG 4 3 MSG 3 2 MSG 2 1 MSG 1 0 MSG 0
Bit Mnemonic Description Message Data This register contains the mailbox data byte pointed at the page message object register. After writing in the page message object register, this byte is equal to the specified message location (in the mailbox) of the pre-defined identifier + index. If auto-incrementation is used, at the end of the data register writing or reading cycle, the mailbox pointer is auto-incremented. The range of the counting is 8 with no end loop (0, 1,..., 7, 0,...)
7-0
MSG7:0
No default value after reset.
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Table 83. CANTCON Register CANTCON (S:A1h) CAN Timer ClockControl
7 TPRESC 7 Bit Number 6 TPRESC 6 5 TPRESC 5 4 TPRESC 4 3 TPRESC 3 2 TPRESC 2 1 TPRESC 1 0 TPRESC 0
Bit Mnemonic Description Timer Prescaler of CAN Timer This register is a prescaler for the main timer upper counter range = 0 to 255. See Figure 55.
7-0
TPRESC7:0
Reset Value = 00h Table 84. CANTIMH Register CANTIMH (S:ADh Read Only) CAN Timer High
7 CANGTIM 15 Bit Number 7-0 6 CANGTIM 14 5 CANGTIM 13 4 CANGTIM 12 3 CANGTIM 11 2 CANGTIM 10 1 0
CANGTIM 9 CANGTIM 8
Bit Mnemonic Description CANGTIM15: High byte of Message Timer 8 See Figure 55.
Reset Value = 0000 0000b Table 85. CANTIML Register CANTIML (S:ACh Read Only) CAN Timer Low
7 6 5 4 3 2 1 0
CANGTIM 7 CANGTIM 6 CANGTIM 5 CANGTIM 4 CANGTIM 3 CANGTIM 2 CANGTIM 1 CANGTIM 0 Bit Number 7-0
Bit Mnemonic Description CANGTIM7:0 Low byte of Message Timer See Figure 55.
Reset Value = 0000 0000b
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Table 86. CANSTMPH Register CANSTMPH (S:AFh Read Only) CAN Stamp Timer High
7 TIMSTMP 15 Bit Number 7-0 6 TIMSTMP 14 5 TIMSTMP 13 4 TIMSTMP 12 3 TIMSTMP 11 2 TIMSTMP 10 1 0
TIMSTMP 9 TIMSTMP 8
Bit Mnemonic Description TIMSTMP15: High byte of Time Stamp 8 See Figure 55.
No default value after reset Table 87. CANSTMPL Register CANSTMPL (S:AEh Read Only) CAN Stamp Timer Low
7 6 5 4 3 2 1 0
TIMSTMP 7 TIMSTMP 6 TIMSTMP 5 TIMSTMP 4 TIMSTMP 3 TIMSTMP 2 TIMSTMP 1 TIMSTMP 0 Bit Number 7-0
Bit Mnemonic Description TIMSTMP7:0 Low byte of Time Stamp See Figure 55.
No default value after reset Table 88. CANTTCH Register CANTTCH (S:A5h Read Only) CAN TTC Timer High
7 TIMTTC 15 Bit Number 7-0 6 TIMTTC 14 5 4 3 TIMTTC 11 2 TIMTTC 10 1 TIMTTC 9 0 TIMTTC 8
TIMTTC 13 TIMTTC 12
Bit Mnemonic Description TIMTTC15:8 High byte of TTC Timer See Figure 55.
Reset Value = 0000 0000b
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Table 89. CANTTCL Register CANTTCL (S:A4h Read Only) CAN TTC Timer Low
7 TIMTTC 7 Bit Number 7-0 6 TIMTTC 6 5 TIMTTC 5 4 TIMTTC 4 3 TIMTTC 3 2 TIMTTC 2 1 TIMTTC 1 0 TIMTTC 0
Bit Mnemonic Description TIMTTC7:0 Low byte of TTC Timer See Figure 55.
Reset Value = 0000 0000b
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Serial Port Interface (SPI)
Features
The Serial Peripheral Interface Module (SPI) allows full-duplex, synchronous, serial communication between the MCU and peripheral devices, including other MCUs. Features of the SPI Module include the following: * * * * * Full-duplex, three-wire synchronous transfers Master or Slave operation Six programmable Master clock rates in master mode Serial clock with programmable polarity and phase Master Mode fault error flag with MCU interrupt capability
Signal Description
Figure 57 shows a typical SPI bus configuration using one Master controller and many Slave peripherals. The bus is made of three wires connecting all the devices. Figure 57. SPI Master/Slaves Interconnection
MISO MOSI SCK SS
Slave 1
MISO MOSI SCK SS
VDD
Master
0 1 2 3
PORT
MISO MOSI SCK SS
Slave 4
Slave 3
MISO MOSI SCK SS
Slave 2
The Master device selects the individual Slave devices by using four pins of a parallel port to control the four SS pins of the Slave devices. Master Output Slave Input (MOSI) This 1-bit signal is directly connected between the Master Device and a Slave Device. The MOSI line is used to transfer data in series from the Master to the Slave. Therefore, it is an output signal from the Master, and an input signal to a Slave. A Byte (8-bit word) is transmitted most significant bit (MSB) first, least significant bit (LSB) last. This 1-bit signal is directly connected between the Slave Device and a Master Device. The MISO line is used to transfer data in series from the Slave to the Master. Therefore, it is an output signal from the Slave, and an input signal to the Master. A Byte (8-bit word) is transmitted most significant bit (MSB) first, least significant bit (LSB) last. This signal is used to synchronize the data transmission both in and out of the devices through their MOSI and MISO lines. It is driven by the Master for eight clock cycles which allows to exchange one Byte on the serial lines. Each Slave peripheral is selected by one Slave Select pin (SS). This signal must stay low for any message for a Slave. It is obvious that only one Master (SS high level) can drive the network. The Master may select each Slave device by software through port pins (Figure 58). To prevent bus conflicts on the MISO line, only one slave should be selected at a time by the Master for a transmission.
Master Input Slave Output (MISO)
SPI Serial Clock (SCK)
Slave Select (SS)
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MISO MOSI SCK SS
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In a Master configuration, the SS line can be used in conjunction with the MODF flag in the SPI Status register (SPSCR) to prevent multiple masters from driving MOSI and SCK (see Error conditions). A high level on the SS pin puts the MISO line of a Slave SPI in a high-impedance state. The SS pin could be used as a general-purpose if the following conditions are met: * The device is configured as a Master and the SSDIS control bit in SPCON is set. This kind of configuration can be found when only one Master is driving the network and there is no way that the SS pin could be pulled low. Therefore, the MODF flag in the SPSCR will never be set(1). The Device is configured as a Slave with CPHA and SSDIS control bits set(2). This kind of configuration can happen when the system includes one Master and one Slave only. Therefore, the device should always be selected and there is no reason that the Master uses the SS pin to select the communicating Slave device.
1. Clearing SSDIS control bit does not clear MODF. 2. Special care should be taken not to set SSDIS control bit when CPHA ='0' because in this mode, the SS is used to start the transmission.
*
Note:
Baud Rate
In Master mode, the baud rate can be selected from a baud rate generator which is controlled by three bits in the SPCON register: SPR2, SPR1 and SPR0.The Master clock is selected from one of seven clock rates resulting from the division of the internal clock by 4, 8, 16, 32, 64 or 128. Table 90 gives the different clock rates selected by SPR2:SPR1:SPR0. In Slave mode, the maximum baud rate allowed on the SCK input is limited to Fsys/4 Table 90. SPI Master Baud Rate Selection
SPR2 0 0 0 0 1 1 1 1 SPR1 0 0 1 1 0 0 1 1 SPR0 0 1 0 1 0 1 0 1 Clock Rate Don't Use FCLK PERIPH /4 FCLK PERIPH/8 FCLK PERIPH /16 FCLK PERIPH /32 FCLK PERIPH /64 FCLK PERIPH /128 Don't Use Baud Rate Divisor (BD) No BRG 4 8 16 32 64 128 No BRG
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Functional Description
Figure 58 shows a detailed structure of the SPI Module.
Figure 58. SPI Module Block Diagram
Internal Bus SPDAT Transmit Data Register Shift Register
7 6 5 4 3 2 1 0
Receive Data Register SPSCR
SPIF OVR MODF SPTE UARTM SPTEIE MODFIE
Pin Control Logic
MOSI MISO
SPI Control
Clock Logic
M S
SCK SS
SPCON
SPR2
SPEN SSDIS MSTR
CPOL
CPHA
SPR1
SPR0
FCLK PERIPH
SPI Interrupt Request
8-bit bus 1-bit signal
Operating Modes
The Serial Peripheral Interface can be configured in one of the two modes: Master mode or Slave mode. The configuration and initialization of the SPI Module is made through two registers: * * * The Serial Peripheral Control register (SPCON) The Serial Peripheral Status and Control Register (SPSCR) The Serial Peripheral DATa register (SPDAT)
Once the SPI is configured, the data exchange is made using: During an SPI transmission, data is simultaneously transmitted (shifted out serially) and received (shifted in serially). A serial clock line (SCK) synchronizes shifting and sampling on the two serial data lines (MOSI and MISO). A Slave Select line (SS) allows individual selection of a Slave SPI device; Slave devices that are not selected do not interfere with SPI bus activities.
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When the Master device transmits data to the Slave device via the MOSI line, the Slave device responds by sending data to the Master device via the MISO line. This implies full-duplex transmission with both data out and data in synchronized with the same clock (Figure 59). Figure 59. Full-Duplex Master-Slave Interconnection
MISO MOSI SPI Clock Generator SCK SS VDD MISO MOSI SCK SS VSS
8-bit Shift register
8-bit Shift register
Master MCU
Slave MCU
Master Mode
The SPI operates in Master mode when the Master bit, MSTR (1), in the SPCON register is set. Only one Master SPI device can initiate transmissions. Software begins the transmission from a Master SPI Module by writing to the Serial Peripheral Data Register (SPDAT). If the shift register is empty, the Byte is immediately transferred to the shift register. The Byte begins shifting out on MOSI pin under the control of the serial clock, SCK. Simultaneously, another Byte shifts in from the Slave on the Master's MISO pin. The transmission ends when the Serial Peripheral transfer data flag, SPIF, in SPSCR becomes set. At the same time that SPIF becomes set, the received Byte from the Slave is transferred to the receive data register in SPDAT. Software clears SPIF by reading the Serial Peripheral Status register (SPSCR) with the SPIF bit set, and then reading the SPDAT. The SPI operates in Slave mode when the Master bit, MSTR (2), in the SPCON register is cleared. Before a data transmission occurs, the Slave Select pin, SS, of the Slave device must be set to'0'. SS must remain low until the transmission is complete. In a Slave SPI Module, data enters the shift register under the control of the SCK from the Master SPI Module. After a Byte enters the shift register, it is immediately transferred to the receive data register in SPDAT, and the SPIF bit is set. To prevent an overflow condition, Slave software must then read the SPDAT before another Byte enters the shift register (3). A Slave SPI must complete the write to the SPDAT (shift register) at least one bus cycle before the Master SPI starts a transmission. If the write to the data register is late, the SPI transmits the data already in the shift register from the previous transmission.
Slave Mode
Transmission Formats
Software can select any of four combinations of serial clock (SCK) phase and polarity using two bits in the SPCON: the Clock Polarity (CPOL (4) ) and the Clock Phase (CPHA4). CPOL defines the default SCK line level in idle state. It has no significant effect on the transmission format. CPHA defines the edges on which the input data are sampled and the edges on which the output data are shifted (Figure 60 and Figure 61). The clock phase and polarity should be identical for the Master SPI device and the communicating Slave device.
1. 2. 3. 4. The SPI Module should be configured as a Master before it is enabled (SPEN set). Also, the Master SPI should be configured before the Slave SPI. The SPI Module should be configured as a Slave before it is enabled (SPEN set). The maximum frequency of the SCK for an SPI configured as a Slave is the bus clock speed. Before writing to the CPOL and CPHA bits, the SPI should be disabled (SPEN ='0').
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Figure 60. Data Transmission Format (CPHA = 0)
SCK Cycle Number SPEN (Internal)
1 2 3 4 5 6 7 8
SCK (CPOL = 0) SCK (CPOL = 1) MOSI (from Master) MISO (from Slave) SS (to Slave) Capture Point
MSB MSB bit6 bit6 bit5 bit5 bit4 bit4 bit3 bit3 bit2 bit2 bit1 bit1 LSB LSB
Figure 61. Data Transmission Format (CPHA = 1)
SCK Cycle Number SPEN (Internal) SCK (CPOL = 0) SCK (CPOL = 1) MOSI (from Master) MISO (from Slave) SS (to Slave) Capture Point
MSB MSB bit6 bit6 bit5 bit5 bit4 bit4 bit3 bit3 bit2 bit2 bit1 bit1 LSB LSB 1 2 3 4 5 6 7 8
Figure 62. CPHA/SS Timing
MISO/MOSI Master SS Slave SS (CPHA = 0) Slave SS (CPHA = 1) Byte 1 Byte 2 Byte 3
As shown in Figure 60, the first SCK edge is the MSB capture strobe. Therefore, the Slave must begin driving its data before the first SCK edge, and a falling edge on the SS pin is used to start the transmission. The SS pin must be toggled high and then low between each Byte transmitted (Figure 62). Figure 61 shows an SPI transmission in which CPHA is '1'. In this case, the Master begins driving its MOSI pin on the first SCK edge. Therefore, the Slave uses the first SCK edge as a start transmission signal. The SS pin can remain low between transmissions (Figure 62). This format may be preferred in systems having only one Master and only one Slave driving the MISO data line. Queuing transmission For an SPI configured in master or slave mode, a queued data byte must be transmitted/received immediately after the previous transmission has completed.
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When a transmission is in progress a new data can be queued and sent as soon as transmission has been completed. So it is possible to transmit bytes without latency, useful in some applications. The SPTE bit in SPSCR is set as long as the transmission buffer is free. It means that the user application can write SPDAT with the data to be transmitted until the SPTE becomes cleared. Figure 63 shows a queuing transmission in master mode. Once the Byte 1 is ready, it is immediately sent on the bus. Meanwhile an other byte is prepared (and the SPTE is cleared), it will be sent at the end of the current transmission. The next data must be ready before the end of the current transmission. Figure 63. Queuing Transmission In Master Mode
SCK MOSI MISO Data
MSB MSB
B6 B6
B5 B5
B4 B4
B3 B3
B2 B2
B1 B1
LSB MSB LSB MSB
B6 B6
B5 B5
B4 B4
B3 B3
B2 B2 Byte 3
B1 B1
LSB LSB
Byte 1
Byte 2
BYTE 1 under transmission
SPTE
BYTE 2 under transmission
In slave mode it is almost the same except it is the external master that start the transmission. Also, in slave mode, if no new data is ready, the last value received will be the next data byte transmitted.
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Error Conditions
The following flags in the SPSCR register indicate the SPI error conditions:
Mode Fault Error (MODF)
Mode Fault error in Master mode SPI indicates that the level on the Slave Select (SS) pin is inconsistent with the actual mode of the device. * Mode fault detection in Master mode:
MODF is set to warn that there may be a multi-master conflict for system control. In this case, the SPI system is affected in the following ways: - - - An SPI receiver/error CPU interrupt request is generated The SPEN bit in SPCON is cleared. This disables the SPI The MSTR bit in SPCON is cleared
Clearing the MODF bit is accomplished by a read of SPSCR register with MODF bit set, followed by a write to the SPCON register. SPEN Control bit may be restored to its original set state after the MODF bit has been cleared. Figure 64. Mode Fault Conditions in Master Mode (Cpha ='1'/Cpol ='0')
SCK cycle # SCK (from master) MOSI (from master) MISO (from slave) SPI enable SS (master) SS (slave)
1 z 0 1 z 0 1 z 0 1 z 0 1 z 0 1 z 0
0
0
1
2
3
0
MSB MSB
B6 B6 B5
MODF detected
MODF detected
Note:
When SS is discarded (SS disabled) it is not possible to detect a MODF error in master mode because the SPI is internally unselected and the SS pin is a general purpose I/O.
*
Mode fault detection in Slave mode
In slave mode, the MODF error is detected when SS goes high during a transmission. A transmission begins when SS goes low and ends once the incoming SCK goes back to its idle level following the shift of the eighteen data bit. A MODF error occurs if a slave is selected (SS is low) and later unselected (SS is high) even if no SCK is sent to that slave. At any time, a '1' on the SS pin of a slave SPI puts the MISO pin in a high impedance state and internal state counter is cleared. Also, the slave SPI ignores all incoming SCK clocks, even if it was already in the middle of a transmission. A new transmission will be performed as soon as SS pin returns low. 136
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Figure 65. Mode Fault Conditions in Slave Mode
SCK cycle # SCK (from master) MOSI (from master) MISO (from slave) SS (slave)
1 z 0 1 z 0 1 z 0 1 z 0
0
0
1
2
3
4
MSB MSB MSB
B6 B6
B5
B4
MODF detected
MODF detected
Note:
when SS is discarded (SS disabled) it is not possible to detect a MODF error in slave mode because the SPI is internally selected. Also the SS pin becomes a general purpose I/O.
OverRun Condition
This error mean that the speed is not adapted for the running application: An OverRun condition occurs when a byte has been received whereas the previous one has not been read by the application yet. The last byte (which generate the overrun error) does not overwrite the unread data so that it can still be read. Therefore, an overrun error always indicates the loss of data.
Interrupts
Three SPI status flags can generate a CPU interrupt requests: Table 91. SPI Interrupts
Flag SPIF (SPI data transfer) MODF (Mode Fault) SPTE (Transmit register empty) Request SPI Transmitter Interrupt Request SPI mode-fault Interrupt Request SPI transmit register empty Interrupt Request
Serial Peripheral data transfer flag, SPIF: This bit is set by hardware when a transfer has been completed. SPIF bit generates transmitter CPU interrupt request only when SPTEIE is disabled. Mode Fault flag, MODF: This bit is set to indicate that the level on the SS is inconsistent with the mode of the SPI (in both master and slave modes). Serial Peripheral Transmit Register empty flag, SPTE: This bit is set when the transmit buffer is empty (other data can be loaded is SPDAT). SPTE bit generates transmitter CPU interrupt request only when SPTEIE is enabled. Note: While using SPTE interruption for "burst mode" transfers (SPTEIE='1'), the user software application should take care to clear SPTEIE, during the last but one data reception (to be able to generate an interrupt on SPIF flag at the end of the last data reception).
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Figure 66. SPI Interrupt Requests Generation
SPIF
SPTEIE SPTE
SPI CPU Interrupt Request
MODFIE MODF
Registers Serial Peripheral Control Register (SPCON)
Three registers in the SPI module provide control, status and data storage functions. These registers are describe in the following paragraphs. * * * * * * The Serial Peripheral Control Register does the following: Selects one of the Master clock rates Configure the SPI Module as Master or Slave Selects serial clock polarity and phase Enables the SPI Module Frees the SS pin for a general-purpose
Table 92 describes this register and explains the use of each bit Table 92. SPCON Register SPCON - Serial Peripheral Control Register (0D4H)
7 SPR2 Bit Number 6 SPEN 5 SSDIS 4 MSTR Description Serial Peripheral Rate 2 7 SPR2 Bit with SPR1 and SPR0 define the clock rate (See bits SPR1 and SPR0 for detail). Serial Peripheral Enable 6 SPEN Cleared to disable the SPI interface (internal reset of the SPI). Set to enable the SPI interface. SS Disable Cleared to enable SS in both Master and Slave modes. 5 SSDIS Set to disable SS in both Master and Slave modes. In Slave mode, this bit has no effect if CPHA ='0'. When SSDIS is set, no MODF interrupt request is generated. Serial Peripheral Master 4 MSTR Cleared to configure the SPI as a Slave. Set to configure the SPI as a Master. 3 CPOL 2 CPHA 1 SPR1 0 SPR0
Bit Mnemonic
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Bit Number Bit Mnemonic Description Clock Polarity 3 CPOL Cleared to have the SCK set to '0' in idle state. Set to have the SCK set to '1' in idle state. Clock Phase 2 CPHA Cleared to have the data sampled when the SCK leaves the idle state (see CPOL). Set to have the data sampled when the SCK returns to idle state (see CPOL). SPR2 1 SPR1 0 0 0 0 1 0 SPR0 1 1 1 SPR1 0 0 1 1 0 0 1 1 SPR0 Serial Peripheral Rate 0 1 0 1 0 1 0 1 Invalid FCLK PERIPH /4 FCLK PERIPH /8 FCLK PERIPH /16 FCLK PERIPH /32 FCLK PERIPH /64 FCLK PERIPH /128 Invalid
Reset Value = 0001 0100b Not bit addressable Serial Peripheral Status Register and Control (SPSCR) The Serial Peripheral Status Register contains flags to signal the following conditions: * * * Data transfer complete Write collision Inconsistent logic level on SS pin (mode fault error)
Table 93. SPSCR Register SPSCR - Serial Peripheral Status and Control register (0D5H)
7 SPIF Bit Number 6 5 OVR 4 MODF 3 SPTE 2 UARTM 1 SPTEIE 0 MODFIE
Bit Mnemonic Description Serial Peripheral Data Transfer Flag
7
SPIF
Cleared by hardware to indicate data transfer is in progress or has been approved by a clearing sequence. Set by hardware to indicate that the data transfer has been completed. This bit is cleared when reading or writing SPDATA after reading SPSCR.
6
-
Reserved The value read from this bit is indeterminate. Do not set this bit. Overrun Error Flag
5
OVR
- Set by hardware when a byte is received whereas SPIF is set (the previous received data is not overwritten). - Cleared by hardware when reading SPSCR
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Bit Number
Bit Mnemonic Description Mode Fault - Set by hardware to indicate that the SS pin is in inappropriate logic level (in both master and slave modes). - Cleared by hardware when reading SPSCR
4
MODF
When MODF error occurred: - In slave mode: SPI interface ignores all transmitted data while SS remains high. A new transmission is perform as soon as SS returns low. - In master mode: SPI interface is disabled (SPEN=0, see description for SPEN bit in SPCON register). Serial Peripheral Transmit register Empty
3
SPTE
- Set by hardware when transmit register is empty (if needed, SPDAT can be loaded with another data). - Cleared by hardware when transmit register is full (no more data should be loaded in SPDAT). Serial Peripheral UART mode
2
UARTM
Set and cleared by software: - Clear: Normal mode, data are transmitted MSB first (default) - Set: UART mode, data are transmitted LSB first. Interrupt Enable for SPTE Set and cleared by software: - Set to enable SPTE interrupt generation (when SPTE goes high, an interrupt is generated). - Clear to disable SPTE interrupt generation Caution: When SPTEIE is set no interrupt generation occurred when SPIF flag goes high. To enable SPIF interrupt again, SPTEIE should be cleared. Interrupt Enable for MODF
1
SPTEIE
0
MODFIE
Set and cleared by software: - Set to enable MODF interrupt generation - Clear to disable MODF interrupt generation
Reset Value = 00X0 XXXXb Not Bit addressable Serial Peripheral DATa Register (SPDAT) The Serial Peripheral Data Register (Table 94) is a read/write buffer for the receive/transmit data register. A Read of the SPDAT returns the value located in the receive buffer and not the content of the shift register. A Write of the SPDAT loads the data to be transmited in the transmit register. Table 94. SPDAT Register SPDAT - Serial Peripheral Data Register (0D6H)
7 R7 6 R6 5 R5 4 R4 3 R3 2 R2 1 R1 0 R0
Reset Value = Indeterminate
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Programmable Counter Array (PCA)
The PCA provides more timing capabilities with less CPU intervention than the standard timer/counters. Its advantages include reduced software overhead and improved accuracy. The PCA consists of a dedicated timer/counter which serves as the time base for an array of five compare/capture modules. Its clock input can be programmed to count any of the following signals: * * * * * * * * PCA clock frequency/6 (see "clock" section) PCA clock frequency/2 Timer 0 overflow External input on ECI (P1.2) rising and/or falling edge capture, software timer, high-speed output, pulse width modulator.
Each compare/capture modules can be programmed in any one of the following modes:
Module 4 can also be programmed as a WatchDog timer. see the "PCA WatchDog Timer" section. When the compare/capture modules are programmed in capture mode, software timer, or high speed output mode, an interrupt can be generated when the module executes its function. All five modules plus the PCA timer overflow share one interrupt vector. The PCA timer/counter and compare/capture modules share Port 1 for external I/Os. These pins are listed below. If the port is not used for the PCA, it can still be used for standard I/O.
PCA Component 16-bit Counter 16-bit Module 0 16-bit Module 1 16-bit Module 2 16-bit Module 3 16-bit Module 4
External I/O Pin P1.2/ECI P1.3/CEX0 P1.4/CEX1 P1.5/CEX2 P1.6/CEX3 P1.7/CEX4
PCA Timer
The PCA timer is a common time base for all five modules (see Figure 67). The timer count source is determined from the CPS1 and CPS0 bits in the CMOD SFR (see Table 8) and can be programmed to run at: * * * * 1/6 the PCA clock frequency. 1/2 the PCA clock frequency. the Timer 0 overflow. the input on the ECI pin (P1.2).
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Figure 67. PCA Timer/Counter
To PCA modules FPca/6 FPca/2 T0 OVF P1.2 CH CL overflow It
16 bit up counter
CIDL Idle
WDTE
CPS1 CPS0
ECF
CMOD 0xD9
CF
CR
CCF4 CCF3 CCF2 CCF1 CCF0
CCON 0xD8
The CMOD register includes three additional bits associated with the PCA. * * * The CIDL bit which allows the PCA to stop during idle mode. The WDTE bit which enables or disables the WatchDog function on module 4. The ECF bit which when set causes an interrupt and the PCA overflow flag CF in CCON register to be set when the PCA timer overflows.
The CCON register contains the run control bit for the PCA and the flags for the PCA timer and each module. * * * The CR bit must be set to run the PCA. The PCA is shut off by clearing this bit. The CF bit is set when the PCA counter overflows and an interrupt will be generated if the ECF bit in CMOD register is set. The CF bit can only be cleared by software. The CCF0:4 bits are the flags for the modules (CCF0 for module0...) and are set by hardware when either a match or a capture occurs. These flags also can be cleared by software.
PCA Modules
Each one of the five compare/capture modules has six possible functions. It can perform: * * * * * * 16-bit Capture, positive-edge triggered 16-bit Capture, negative-edge triggered 16-bit Capture, both positive and negative-edge triggered 16-bit Software Timer 16-bit High Speed Output 8-bit Pulse Width Modulator.
In addition module 4 can be used as a WatchDog Timer.
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Each module in the PCA has a special function register associated with it (CCAPM0 for module 0 ...). The CCAPM0:4 registers contain the bits that control the mode that each module will operate in. * * * The ECCF bit enables the CCF flag in the CCON register to generate an interrupt when a match or compare occurs in the associated module. The PWM bit enables the pulse width modulation mode. The TOG bit when set causes the CEX output associated with the module to toggle when there is a match between the PCA counter and the module's capture/compare register. The match bit MAT when set will cause the CCFn bit in the CCON register to be set when there is a match between the PCA counter and the module's capture/compare register. The two bits CAPN and CAPP in CCAPMn register determine the edge that a capture input will be active on. The CAPN bit enables the negative edge, and the CAPP bit enables the positive edge. If both bits are set both edges will be enabled. The bit ECOM in CCAPM register when set enables the comparator function.
*
*
*
PCA Interrupt
Figure 68. PCA Interrupt System
CF PCA Timer/Counter CR CCF4 CCF3 CCF2 CCF1 CCF0 CCON
Module 0 Module 1 Module 2 Module 3 Module 4
To Interrupt
ECF
CMOD.0
ECCFn
CCAPMn.0
EC
IEN0.6
EA
IEN0.7
PCA Capture Mode
To use one of the PCA modules in capture mode either one or both of the CCAPM bits CAPN and CAPP for that module must be set. The external CEX input for the module (on port 1) is sampled for a transition. When a valid transition occurs the PCA hardware loads the value of the PCA counter registers (CH and CL) into the module's capture registers (CCAPnL and CCAPnH). If the CCFn bit for the module in the CCON SFR and the ECCFn bit in the CCAPMn SFR are set then an interrupt will be generated.
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Figure 69. PCA Capture Mode PCA Counter
CH CL (8bits) (8bits)
CEXn n = 0, 4
CCAPnH CCAPnL
CCFn CCON
CAPMn ECOMn CAPPn CAPNn MATn TOGn PWMn ECCFn
PCA Interrupt Request
7
0 CCAPMn Register (n = 0, 4)
16-bit Software Timer Mode
The PCA modules can be used as software timers by setting both the ECOM and MAT bits in the modules CCAPMn register. The PCA timer will be compared to the module's capture registers and when a match occurs an interrupt will occur if the CCFn (CCON SFR) and the ECCFn (CCAPMn SFR) bits for the module are both set.
Figure 70. PCA 16-bit Software Timer and High Speed Output Mode
PCA Counter CH CL (8 bits) (8 bits) Compare/Capture Module CCAPnL CCAPnH (8 bits) (8 bits) Match 16-Bit Comparator Enable CCFn CCON reg Toggle CEXn PCA Interrupt Request
CAPMn
ECOMn
CAPPn
CAPNn MATn
TOGn
PWMn ECCFn
7 "0" Reset Write to CCAPnL Write to CCAPnH "1"
0 CCAPMn Register (n = 0, 4) For software Timer mode, set ECOMn and MATn. For high speed output mode, set ECOMn, MATn and TOGn.
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High Speed Output Mode In this mode the CEX output (on port 1) associated with the PCA module will toggle
each time a match occurs between the PCA counter and the module's capture registers. To activate this mode the TOG, MAT, and ECOM bits in the module's CCAPMn SFR must be set. Figure 71. PCA High Speed Output Mode
CF Write to CCAPnH Write to CCAPnL "0" "1" Enable 16-bit comparator Reset PCA IT CCAPnH CCAPnL Match CR CCF4 CCF3 CCF2 CCF1 CCF0 CCON 0xD8
CH PCA counter/timer
CL
CEXn
ECOMn CAPPn CAPNn MATn TOGn PWMn ECCFn
CCAPMn, n = 0 to 4 0xDA to 0xDE
Pulse Width Modulator Mode
All the PCA modules can be used as PWM outputs. The output frequency depends on the source for the PCA timer. All the modules will have the same output frequency because they all share the PCA timer. The duty cycle of each module is independently variable using the module's capture register CCAPLn. When the value of the PCA CL SFR is less than the value in the module's CCAPLn SFR the output will be low, when it is equal to or greater than it, the output will be high. When CL overflows from FF to 00, CCAPLn is reloaded with the value in CCAPHn. the allows the PWM to be updated without glitches. The PWM and ECOM bits in the module's CCAPMn register must be set to enable the PWM mode.
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Figure 72. PCA PWM Mode CCAPnH
CL rolls over from FFh TO 00h loads CCAPnH contents into CCAPnL
CCAPnL "0" CL (8 bits) 8-Bit Comparator CL < CCAPnL CEX CL > = CCAPnL "1"
ECOMn
CCAPMn.6
PWMn
CCAPMn.1
PCA WatchDog Timer
An on-board WatchDog timer is available with the PCA to improve system reliability without increasing chip count. WatchDog timers are useful for systems that are sensitive to noise, power glitches, or electrostatic discharge. Module 4 is the only PCA module that can be programmed as a WatchDog. However, this module can still be used for other modes if the WatchDog is not needed. The user pre-loads a 16-bit value in the compare registers. Just like the other compare modes, this 16-bit value is compared to the PCA timer value. If a match is allowed to occur, an internal reset will be generated. This will not cause the RST pin to be driven high. To hold off the reset, the user has three options: * * * periodically change the compare value so it will never match the PCA timer, periodically change the PCA timer value so it will never match the compare values, or disable the WatchDog by clearing the WDTE bit before a match occurs and then reenable it.
The first two options are more reliable because the WatchDog timer is never disabled as in the third option. If the program counter ever goes astray, a match will eventually occur and cause an internal reset. If other PCA modules are being used the second option not recommended either. Remember, the PCA timer is the time base for all modules; changing the time base for other modules would not be a good idea. Thus, in most applications the first solution is the best option.
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PCA Registers
Table 95. CMOD Register CMOD (S:D9h) PCA Counter Mode Register
7 CIDL Bit Number 7 6 WDTE 5 4 3 2 CPS1 1 CPS0 0 ECF
Bit Mnemonic Description CIDL PCA Counter Idle Control bit Clear to let the PCA run during Idle mode. Set to stop the PCA when Idle mode is invoked. WatchDog Timer Enable Clear to disable WatchDog Timer function on PCA Module 4, Set to enable it. Reserved The value read from this bit is indeterminate. Do not set this bit. Reserved The value read from this bit is indeterminate. Do not set this bit. Reserved The value read from this bit is indeterminate. Do not set this bit. EWC Count Pulse Select bits CPS1 CPS0 Clock source 0 0 Internal Clock, FPca/6 0 1 Internal Clock, FPca/2 1 0 Timer 0 overflow 1 1 External clock at ECI/P1.2 pin (Max. Rate = FPca/4) Reserved The value read from this bit is indeterminate. Do not set this bit. Enable PCA Counter Overflow Interrupt bit Clear to disable CF bit in CCON register to generate an interrupt. Set to enable CF bit in CCON register to generate an interrupt.
6
WDTE
5 4 3
-
2
CPS1
1
CPS0
0
ECF
Reset Value = 00XX X000b
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Table 96. CCON Register CCON (S:D8h) PCA Counter Control Register
7 CF Bit Number 6 CR 5 4 CCF4 3 CCF3 2 CCF2 1 CCF1 0 CCF0
Bit Mnemonic Description PCA Timer/Counter Overflow flag Set by hardware when the PCA Timer/Counter rolls over. This generates a PCA interrupt request if the ECF bit in CMOD register is set. Must be cleared by software. PCA Timer/Counter Run Control bit Clear to turn the PCA Timer/Counter off. Set to turn the PCA Timer/Counter on. Reserved The value read from this bit is indeterminate. Do not set this bit. PCA Module 4 Compare/Capture flag Set by hardware when a match or capture occurs. This generates a PCA interrupt request if the ECCF 4 bit in CCAPM 4 register is set. Must be cleared by software. PCA Module 3 Compare/Capture flag Set by hardware when a match or capture occurs. This generates a PCA interrupt request if the ECCF 3 bit in CCAPM 3 register is set. Must be cleared by software. PCA Module 2 Compare/Capture flag Set by hardware when a match or capture occurs. This generates a PCA interrupt request if the ECCF 2 bit in CCAPM 2 register is set. Must be cleared by software. PCA Module 1 Compare/Capture flag Set by hardware when a match or capture occurs. This generates a PCA interrupt request if the ECCF 1 bit in CCAPM 1 register is set. Must be cleared by software. PCA Module 0 Compare/Capture flag Set by hardware when a match or capture occurs. This generates a PCA interrupt request if the ECCF 0 bit in CCAPM 0 register is set. Must be cleared by software.
7
CF
6
CR
5
-
4
CCF4
3
CCF3
2
CCF2
1
CCF1
0
CCF0
Reset Value = 00X0 0000b
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Table 97. CCAPnH Registers CCAP0H (S:FAh) CCAP1H (S:FBh) CCAP2H (S:FCh) CCAP3H (S:FDh) CCAP4H (S:FEh) PCA High Byte Compare/Capture Module n Register (n=0..4)
7 CCAPnH 7 Bit Number 7:0 6 CCAPnH 6 5 CCAPnH 5 4 CCAPnH 4 3 CCAPnH 3 2 CCAPnH 2 1 CCAPnH 1 0 CCAPnH 0
Bit Mnemonic Description CCAPnH 7:0 High byte of EWC-PCA comparison or capture values
Reset Value = 0000 0000b Table 98. CCAPnL Registers CCAP0L (S:EAh) CCAP1L (S:EBh) CCAP2L (S:ECh) CCAP3L (S:EDh) CCAP4L (S:EEh) PCA Low Byte Compare/Capture Module n Register (n=0..4)
7 CCAPnL 7 Bit Number 7:0 6 CCAPnL 6 5 CCAPnL 5 4 CCAPnL 4 3 CCAPnL 3 2 CCAPnL 2 1 CCAPnL 1 0 CCAPnL 0
Bit Mnemonic Description CCAPnL 7:0 Low byte of EWC-PCA comparison or capture values
Reset Value = 0000 0000b
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Table 99. CCAPMn Registers CCAPM0 (S:DAh) CCAPM1 (S:DBh) CCAPM2 (S:DCh) CCAPM3 (S:DDh) CCAPM4 (S:DEh) PCA Compare/Capture Module n Mode registers (n=0..4)
7 Bit Number 7 6 ECOMn 5 CAPPn 4 CAPNn 3 MATn 2 TOGn 1 PWMn 0 ECCFn
Bit Mnemonic Description Reserved The Value read from this bit is indeterminate. Do not set this bit. Enable Compare Mode Module x bit Clear to disable the Compare function. Set to enable the Compare function. The Compare function is used to implement the software Timer, the high-speed output, the Pulse Width Modulator (PWM) and the WatchDog Timer (WDT). Capture Mode (Positive) Module x bit Clear to disable the Capture function triggered by a positive edge on CEXx pin. Set to enable the Capture function triggered by a positive edge on CEXx pin Capture Mode (Negative) Module x bit Clear to disable the Capture function triggered by a negative edge on CEXx pin. Set to enable the Capture function triggered by a negative edge on CEXx pin. Match Module x bit Set when a match of the PCA Counter with the Compare/Capture register sets CCFx bit in CCON register, flagging an interrupt. Toggle Module x bit The toggle mode is configured by setting ECOMx, MATx and TOGx bits. Set when a match of the PCA Counter with the Compare/Capture register toggles the CEXx pin. Pulse Width Modulation Module x Mode bit Set to configure the module x as an 8-bit Pulse Width Modulator with output waveform on CEXx pin. Enable CCFx Interrupt bit Clear to disable CCFx bit in CCON register to generate an interrupt request. Set to enable CCFx bit in CCON register to generate an interrupt request.
6
ECOMn
5
CAPPn
4
CAPNn
3
MATn
2
TOGn
1
PWMn
0
ECCFn
Reset Value = X000 0000b
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Table 100. CH Register CH (S:F9h) PCA Counter Register High Value
7 CH 7 Bit Number 7:0 6 CH 6 5 CH 5 4 CH 4 3 CH 3 2 CH 2 1 CH 1 0 CH 0
Bit Mnemonic Description CH 7:0 High byte of Timer/Counter
Reset Value = 0000 00000b Table 101. CL Register CL (S:E9h) PCA counter Register Low Value
7 CL 7 Bit Number 7:0 6 CL 6 5 CL 5 4 CL 4 3 CL 3 2 CL 2 1 CL 1 0 CL 0
Bit Mnemonic Description CL0 7:0 Low byte of Timer/Counter
Reset Value = 0000 00000b
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Analog-to-Digital Converter (ADC)
This section describes the on-chip 10 bit analog-to-digital converter of the AT89C51CC03. Eight ADC channels are available for sampling of the external sources AN0 to AN7. An analog multiplexer allows the single ADC converter to select one from the 8 ADC channels as ADC input voltage (ADCIN). ADCIN is converted by the 10-bit cascaded potentiometric ADC. Two kinds of conversion are available: - Standard conversion (8 bits). - Precision conversion (10 bits) (Up to 85C only). For the precision conversion, set bit PSIDLE in ADCON register and start conversion. The device is in a pseudo-idle mode, the CPU does not run but the peripherals are always running. This mode allows digital noise to be as low as possible, to ensure high precision conversion. For this mode it is necessary to work with end of conversion interrupt, which is the only way to wake the device up. If another interrupt occurs during the precision conversion, it will be treated only after this conversion is ended.
Features
* * * * * * * * * *
8 channels with multiplexed inputs 10-bit cascaded potentiometric ADC Conversion time 16 micro-seconds (typ.) Zero Error (offset) 2 LSB max Positive External Reference Voltage Range (VREF) 2.4 to 3.0Volt (typ.) ADCIN Range 0 to 3Volt Integral non-linearity typical 1 LSB, max. 2 LSB Differential non-linearity typical 0.5 LSB, max. 1 LSB Conversion Complete Flag or Conversion Complete Interrupt Selectable ADC Clock
ADC Port1 I/O Functions
Port 1 pins are general I/O that are shared with the ADC channels. The channel select bit in ADCF register define which ADC channel/port1 pin will be used as ADCIN. The remaining ADC channels/port1 pins can be used as general-purpose I/O or as the alternate function that is available. A conversion launched on a channel which are not selected on ADCF register will not have any effect.
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Figure 73. ADC Description
ADCON.5 ADCON.3
ADEN
ADC CLOCK
ADSST
ADCON.4
CONTROL
ADEOC EADC
ADC Interrupt Request
IEN1.1
AN0/P1.0 AN1/P1.1 AN2/P1.2 AN3/P1.3 AN4/P1.4 AN5/P1.5 AN6/P1.6 AN7/P1.7
000 001 010 011 100 101 110 111
AVSS
ADCIN
8
+ SAR 10 2
ADDH ADDL
Sample and Hold R/2R DAC
SCH2
ADCON.2
SCH1
ADCON.1
SCH0
ADCON.0
VAREF VAGND
Figure 74 shows the timing diagram of a complete conversion. For simplicity, the figure depicts the waveforms in idealized form and do not provide precise timing information. For ADC characteristics and timing parameters refer to the Section "AC Characteristics" of the AT89C51CC03 datasheet. Figure 74. Timing Diagram CLK ADEN
TSETUP
ADSST
TCONV
ADEOC
Note:
Tsetup min = 4 us Tconv=11 clock ADC = 1sample and hold + 10 bit conversion The user must ensure that 4 us minimum time between setting ADEN and the start of the first conversion.
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ADC Converter Operation
A start of single A/D conversion is triggered by setting bit ADSST (ADCON.3). After completion of the A/D conversion, the ADSST bit is cleared by hardware. The end-of-conversion flag ADEOC (ADCON.4) is set when the value of conversion is available in ADDH and ADDL, it must be cleared by software. If the bit EADC (IEN1.1) is set, an interrupt occur when flag ADEOC is set (see Figure 76). Clear this flag for rearming the interrupt. The bits SCH0 to SCH2 in ADCON register are used for the analog input channel selection. Table 102. Selected Analog input
SCH2 0 0 0 0 1 1 1 1 SCH1 0 0 1 1 0 0 1 1 SCH0 0 1 0 1 0 1 0 1 Selected Analog input AN0 AN1 AN2 AN3 AN4 AN5 AN6 AN7
Voltage Conversion
When the ADCIN is equals to VAREF the ADC converts the signal to 3FFh (full scale). If the input voltage equals VAGND, the ADC converts it to 000h. Input voltage between VAREF and VAGND are a straight-line linear conversion. All other voltages will result in 3FFh if greater than VAREF and 000h if less than VAGND. Note that ADCIN should not exceed VAREF absolute maximum range! (See section "AC-DC")
Clock Selection
The ADC clock is the same as CPU. The maximum clock frequency is defined in the DC parameters for A/D converter. A prescaler is featured (ADCCLH) to generate the ADC clock from the oscillator frequency. FADC = Fperiph / 4 (or 2 in X2 mode) x PRS if PRS = 0 then FADC = Fperiph / 64 if PRS > 0 then FADC = Fperiph / 2 x PRS
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Figure 75. A/D Converter Clock
CPU CLOCK
/2
Prescaler ADCLK
ADC Clock
A/D Converter
CPU Core Clock Symbol
ADC Standby Mode IT ADC Management
When the ADC is not used, it is possible to set it in standby mode by clearing bit ADEN in ADCON register. In this mode its power dissipation is about 1 W. An interrupt end-of-conversion will occurs when the bit ADEOC is activated and the bit EADC is set. For re-arming the interrupt the bit ADEOC must be cleared by software. Figure 76. ADC Interrupt Structure
ADEOC
ADCON.2
ADCI EADC
IEN1.1
Routines examples
1. Configure P1.2 and P1.3 in ADC channels
// configure channel P1.2 and P1.3 for ADC ADCF = 0Ch // Enable the ADC ADCON = 20h
2. Start a standard conversion
// The variable "channel" contains the channel to convert // The variable "value_converted" is an unsigned int // Clear the field SCH[2:0] ADCON and = F8h // Select channel ADCON | = channel // Start conversion in standard mode ADCON | = 08h // Wait flag End of conversion while((ADCON and 01h)! = 01h) // Clear the End of conversion flag ADCON and = EFh // read the value value_converted = (ADDH << 2)+(ADDL)
3. Start a precision conversion (need interrupt ADC)
// The variable "channel" contains the channel to convert // Enable ADC
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EADC = 1 // clear the field SCH[2:0] ADCON and = F8h // Select the channel ADCON | = channel // Start conversion in precision mode ADCON | = 48h
Note:
to enable the ADC interrupt: EA = 1
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Registers
Table 103. ADCF Register ADCF (S:F6h) ADC Configuration
7 CH 7 Bit Number 7-0 6 CH 6 5 CH 5 4 CH 4 3 CH 3 2 CH 2 1 CH 1 0 CH 0
Bit Mnemonic Description CH 0:7 Channel Configuration Set to use P1.x as ADC input. Clear to use P1.x as standart I/O port.
Reset Value =0000 0000b Table 104. ADCON Register ADCON (S:F3h) ADC Control Register
7 Bit Number 7 6 6 PSIDLE 5 ADEN 4 ADEOC 3 ADSST 2 SCH2 1 SCH1 0 SCH0
Bit Mnemonic Description PSIDLE Pseudo Idle Mode (Best Precision) Set to put in idle mode during conversion Clear to convert without idle mode. Enable/Standby Mode Set to enable ADC Clear for Standby mode (power dissipation 1 uW). End Of Conversion Set by hardware when ADC result is ready to be read. This flag can generate an interrupt. Must be cleared by software. Start and Status Set to start an A/D conversion. Cleared by hardware after completion of the conversion Selection of Channel to Convert see Table 102
5
ADEN
4
ADEOC
3
ADSST
2-0
SCH2:0
Reset Value =X000 0000b
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Table 105. ADCLK Register ADCLK (S:F2h) ADC Clock Prescaler
7 Bit Number 7-5 4-0 6 5 4 PRS 4 3 PRS 3 2 PRS 2 1 PRS 1 0 PRS 0
Bit Mnemonic Description PRS4:0 Reserved The value read from these bits are indeterminate. Do not set these bits. Clock Prescaler See Note (1)
Reset Value = XXX0 0000b
Note: 1. In X1 mode: For PRS > 0 FADC = FXTAL 4xPRS For PRS = 0 FADC = FXTAL 128 In X2 mode: For PRS > 0 FADC = FXTAL 2xPRS For PRS = 0 FADC = FXTAL 64
Table 106. ADDH Register ADDH (S:F5h Read Only) ADC Data High Byte Register
7 ADAT 9 Bit Number 7-0 6 ADAT 8 5 ADAT 7 4 ADAT 6 3 ADAT 5 2 ADAT 4 1 ADAT 3 0 ADAT 2
Bit Mnemonic Description ADAT9:2 ADC result bits 9-2
Reset Value = 00h Table 107. ADDL Register ADDL (S:F4h Read Only) ADC Data Low Byte Register
7 6 5 4 3 2 1 ADAT 1 0 ADAT 0
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Bit Number 7-2 1-0 Bit Mnemonic Description ADAT1:0 Reserved The value read from these bits are indeterminate. Do not set these bits. ADC result bits 1-0
Reset Value = 00h
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Interrupt System
Introduction
The CAN Controller has a total of 10 interrupt vectors: two external interrupts (INT0 and INT1), three timer interrupts (timers 0, 1 and 2), a serial port interrupt, a PCA, a CAN interrupt, a timer overrun interrupt and an ADC. These interrupts are shown below.
Highest Priority Interrupts
Figure 77. Interrupt Control System
INT0# External Interrupt 0 EX0
IEN0.0
00 01 10 11 00 01 10 11 00 01 10 11 00 01 10 11 00 01 10 11 00 01 10 11
Timer 0 ET0 INT1# External Interrupt 1
IEN0.1
EX1
IEN0.2
Timer 1 ET1 CEX0:5 PCA
IEN0.3
EC TxD RxD ES
IEN0.4
UART
IEN0.6
Timer 2 ET2
IEN0.5
00 01 10 11
TxDC RxDC
CAN controller ECAN
IEN1.0
00 01 10 11
AIN1:0
A to D Converter EADC
IEN1.1
00 01 10 11 00 01 10 11 00 01 10 11
CAN Timer ETIM SPI Controller
IEN1.2
ESPI
IEN1.3
EA
IEN0.7
IPH/L Priority Enable Lowest Priority Interrupts
Interrupt Enable
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Each of the interrupt sources can be individually enabled or disabled by setting or clearing a bit in the Interrupt Enable register. This register also contains a global disable bit which must be cleared to disable all the interrupts at the same time. Each interrupt source can also be individually programmed to one of four priority levels by setting or clearing a bit in the Interrupt Priority registers. The Table below shows the bit values and priority levels associated with each combination. Table 108. Priority Level Bit Values
IPH.x 0 0 1 1 IPL.x 0 1 0 1 Interrupt Level Priority 0 (Lowest) 1 2 3 (Highest)
A low-priority interrupt can be interrupted by a high priority interrupt but not by another low-priority interrupt. A high-priority interrupt cannot be interrupted by any other interrupt source. If two interrupt requests of different priority levels are received simultaneously, the request of the higher priority level is serviced. If interrupt requests of the same priority level are received simultaneously, an internal polling sequence determines which request is serviced. Thus within each priority level there is a second priority structure determined by the polling sequence, see Table 109. Table 109. Interrupt priority Within level
Interrupt Name external interrupt (INT0) Timer0 (TF0) external interrupt (INT1) Timer1 (TF1) PCA (CF or CCFn) UART (RI or TI) Timer2 (TF2) CAN (Txok, Rxok, Err or OvrBuf) ADC (ADCI) CAN Timer Overflow (OVRTIM) SPI interrupt Interrupt Address Vector 0003h 000Bh 0013h 001Bh 0033h 0023h 002Bh 003Bh 0043h 004Bh 0053h Priority Number 1 2 3 4 5 6 7 8 9 10 11
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Registers
Table 110. IEN0 Register IEN0 (S:A8h) Interrupt Enable Register
7 EA Bit Number 6 EC 5 ET2 4 ES 3 ET1 2 EX1 1 ET0 0 EX0
Bit Mnemonic Description Enable All Interrupt bit Clear to disable all interrupts. Set to enable all interrupts. If EA=1, each interrupt source is individually enabled or disabled by setting or clearing its interrupt enable bit. PCA Interrupt Enable Clear to disable the PCA interrupt. Set to enable the PCA interrupt. Timer 2 Overflow Interrupt Enable bit Clear to disable Timer 2 overflow interrupt. Set to enable Timer 2 overflow interrupt. Serial Port Enable bit Clear to disable serial port interrupt. Set to enable serial port interrupt. Timer 1 Overflow Interrupt Enable bit Clear to disable timer 1 overflow interrupt. Set to enable timer 1 overflow interrupt. External Interrupt 1 Enable bit Clear to disable external interrupt 1. Set to enable external interrupt 1. Timer 0 Overflow Interrupt Enable bit Clear to disable timer 0 overflow interrupt. Set to enable timer 0 overflow interrupt. External Interrupt 0 Enable bit Clear to disable external interrupt 0. Set to enable external interrupt 0.
7
EA
6
EC
5
ET2
4
ES
3
ET1
2
EX1
1
ET0
0
EX0
Reset Value = 0000 0000b bit addressable
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Table 111. IEN1 Register IEN1 (S:E8h) Interrupt Enable Register
7 Bit Number 7 6 5 4 6 5 4 3 ESPI 2 ETIM 1 EADC 0 ECAN
Bit Mnemonic Description Reserved The value read from this bit is indeterminate. Do not set this bit. Reserved The value read from this bit is indeterminate. Do not set this bit. Reserved The value read from this bit is indeterminate. Do not set this bit. Reserved The value read from this bit is indeterminate. Do not set this bit. SPI Interrupt Enable bit Clear to disable the SPI interrupt. Set to enable the SPI interrupt. TImer Overrun Interrupt Enable bit Clear to disable the timer overrun interrupt. Set to enable the timer overrun interrupt. ADC Interrupt Enable bit Clear to disable the ADC interrupt. Set to enable the ADC interrupt. CAN Interrupt Enable bit Clear to disable the CAN interrupt. Set to enable the CAN interrupt.
3
ESPI
2
ETIM
1
EADC
0
ECAN
Reset Value = xxxx 0000b bit addressable
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Table 112. IPL0 Register IPL0 (S:B8h) Interrupt Enable Register
7 Bit Number 7 6 5 4 3 2 1 0 6 PPC 5 PT2 4 PS 3 PT1 2 PX1 1 PT0 0 PX0
Bit Mnemonic Description PPC PT2 PS PT1 PX1 PT0 PX0 Reserved The value read from this bit is indeterminate. Do not set this bit. PCA Interrupt Priority bit Refer to PPCH for priority level Timer 2 Overflow Interrupt Priority bit Refer to PT2H for priority level. Serial Port Priority bit Refer to PSH for priority level. Timer 1 Overflow Interrupt Priority bit Refer to PT1H for priority level. External Interrupt 1 Priority bit Refer to PX1H for priority level. Timer 0 Overflow Interrupt Priority bit Refer to PT0H for priority level. External Interrupt 0 Priority bit Refer to PX0H for priority level.
Reset Value = X000 0000b bit addressable
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Table 113. IPL1 Register IPL1 (S:F8h) Interrupt Priority Low Register 1
7 Bit Number 7 6 5 4 3 2 1 0 6 5 4 3 SPIL 2 POVRL 1 PADCL 0 PCANL
Bit Mnemonic Description SPIL POVRL PADCL PCANL Reserved The value read from this bit is indeterminate. Do not set this bit. Reserved The value read from this bit is indeterminate. Do not set this bit. Reserved The value read from this bit is indeterminate. Do not set this bit. Reserved The value read from this bit is indeterminate. Do not set this bit. SPI Interrupt Priority Level Less Significant Bit Refer to SPIH for priority level. Timer Overrun Interrupt Priority Level Less Significant Bit Refer to PI2CH for priority level. ADC Interrupt Priority Level Less Significant Bit Refer to PSPIH for priority level. CAN Interrupt Priority Level Less Significant Bit Refer to PKBH for priority level.
Reset Value = XXXX 0000b bit addressable
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Table 114. IPL0 Register IPH0 (B7h) Interrupt High Priority Register
7 Bit Number 7 6 PPCH 5 PT2H 4 PSH 3 PT1H 2 PX1H 1 PT0H 0 PX0H
Bit Mnemonic Description Reserved The value read from this bit is indeterminate. Do not set this bit. PCA Interrupt Priority Level Most Significant bit PPCH PPC Priority level 0 0 Lowest 0 1 1 0 1 1 Highest priority Timer 2 Overflow Interrupt High Priority bit PT2H PT2 Priority Level 0 0 Lowest 0 1 1 0 1 1 Highest Serial Port High Priority bit PSH PS Priority Level 0 0 Lowest 0 1 1 0 1 1 Highest Timer 1 Overflow Interrupt High Priority bit PT1H PT1 Priority Level 0 0 Lowest 0 1 1 0 1 1 Highest External Interrupt 1 High Priority bit PX1H PX1 Priority Level 0 0 Lowest 0 1 1 0 1 1 Highest Timer 0 Overflow Interrupt High Priority bit PT0H PT0 Priority Level 0 0 Lowest 0 1 1 0 1 1 Highest External Interrupt 0 high priority bit PX0H PX0 Priority Level 0 0 Lowest 0 1 1 0 1 1 Highest
6
PPCH
5
PT2H
4
PSH
3
PT1H
2
PX1H
1
PT0H
0
PX0H
Reset Value = X000 0000b
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Table 115. IPH1 Register IPH1 (S:F7h) Interrupt High Priority Register 1
7 Bit Number 7 6 5 4 6 5 4 3 SPIH 2 POVRH 1 PADCH 0 PCANH
Bit Mnemonic Description Reserved The value read from this bit is indeterminate. Do not set this bit. Reserved The value read from this bit is indeterminate. Do not set this bit. Reserved The value read from this bit is indeterminate. Do not set this bit. Reserved The value read from this bit is indeterminate. Do not set this bit. SPI Interrupt Priority Level Most Significant bit SPIH SPIL Priority level 0 0 Lowest 0 1 1 0 1 1 Highest Timer overrun Interrupt Priority Level Most Significant bit POVRH POVRL Priority level 0 0 Lowest 0 1 1 0 1 1 Highest ADC Interrupt Priority Level Most Significant bit PADCH PADCL Priority level 0 0 Lowest 0 1 1 0 1 1 Highest CAN Interrupt Priority Level Most Significant bit PCANH PCANL Priority level 0 0 Lowest 0 1 1 0 1 1 Highest
3
SPIH
2
POVRH
1
PADCH
0
PCANH
Reset Value = XXXX 0000b
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Electrical Characteristics
Absolute Maximum Ratings
Ambiant Temperature Under Bias: I = industrial........................................................-40C to 85C A = automotive..................................................-40C to +125C Voltage on VCC from VSS ......................................-0.5V to + 6V Voltage on Any Pin from VSS..................... -0.5V to VCC + 0.2V Power Dissipation .............................................................. 1 W Note: Stresses at or above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions may affect device reliability. The power dissipation is based on the maximum allowable die temperature and the thermal resistance of the package.
ICCOP Test Conditions
Power Consumption Management Since the introduction of the first C51 device, every manufacturer made operating ICC measurements under Reset, which made sense for the designs where the CPU was running under reset. In our new devices, the CPU is no longer active during reset, so the power consumption is very low but not representative of what will happen in the customer system. Thus, while keeping measurements under Reset, we present a new way to measure the operating ICC. Using an internal test ROM, the following code is executed. Label: SJMP Label (80FE) Ports 1 and 4 are disconnected, RST = Vcc, XTAL2 is not connected and XTAL1 is driven by the clock. This is much more representative of the real operating Icc.
DC Parameters for Standard Voltage
Industrial TA = -40C to +85C; VSS = 0V; Automotive TA = -40C to +125C; VSS = 0V VCC =3.0V to 5.5V and F = 0 to 40 MHz (both internal and external code execution) VCC =4.5V to 5.5V and F = 0 to 60 MHz (internal code execution only) Table 116. DC Parameters in Standard Voltage
Symbol VIL VIH VIH1 VOL Parameter Input Low Voltage Input High Voltage except XTAL1, RST Input High Voltage, XTAL1, RST Min -0.5 0.2 VCC + 0.9 0.7 VCC
(6)
Typ(5)
Max 0.2Vcc - 0.1 VCC + 0.5 VCC + 0.5 0.3 0.45 1.0 0.3
Unit V V V V V V V V V
Test Conditions
IOL = 100 A(4) IOL = 1.6 mA(4) IOL = 3.5 mA(4) IOL = 200 A(4) IOL = 3.2 mA(4) IOL = 7.0 mA(4)
Output Low Voltage, ports 1, 2, 3 and 4
VOL1
Output Low Voltage, port 0, ALE, PSEN (6)
0.45 1.0
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Table 116. DC Parameters in Standard Voltage (Continued)
Symbol Parameter Min VCC - 0.3 VOH Output High Voltage, ports 1, 2, 3, and 4 VCC - 0.7 VCC - 1.5 VCC - 0.3 VOH1 Output High Voltage, port 0, ALE, PSEN VCC - 0.7 VCC - 1.5 RRST IIL ILI ITL CIO RST Pulldown Resistor Logical 0 Input Current ports 1, 2, 3 and 4 Input Leakage Current Logical 1 to 0 Transition Current, ports 1, 2, 3 and 4 Capacitance of I/O Buffer Power-down Current Industrial IPD Power-down Current Automotive Power Supply Current 75 100 ICCOP = 0.4 Frequency (MHz) + 8 ICCIDLE = 0.2 Frequency (MHz) + 8 0.8 x Frequency (MHz) + 15 20 100 200 -50 10 -650 10 150 350 Typ(5) Max Unit V V V Test Conditions IOH = -10 A IOH = -30 A IOH = -60 A VCC = 3V to 5.5V IOH = -200 A IOH = -3.2 mA IOH = -7.0 mA VCC = 5V 10%
V V V k A A A pF A A mA
Vin = 0.45V 0.45V < Vin < VCC Vin = 2.0V Fc = 1 MHz TA = 25C 3V < VCC < 5.5V(3) 3V < VCC < 5.5V(3) Vcc = 5.5V(1)(2)
ICC
ICCWRITE
Power Supply Current on flash or EEdata write
mA
VCC = 5.5V
Notes:
1. Operating ICC is measured with all output pins disconnected; XTAL1 driven with TCLCH, TCHCL = 5 ns (see Figure 81.), VIL = VSS + 0.5V, VIH = VCC - 0.5V; XTAL2 N.C.; EA = RST = Port 0 = VCC. ICC would be slightly higher if a crystal oscillator used (see Figure 78.). 2. Idle ICC is measured with all output pins disconnected; XTAL1 driven with TCLCH, TCHCL = 5 ns, VIL = VSS + 0.5V, VIH = VCC 0.5V; XTAL2 N.C; Port 0 = VCC; EA = RST = VSS (see Figure 79.). 3. Power-down ICC is measured with all output pins disconnected; EA = VCC, PORT 0 = VCC; XTAL2 NC.; RST = VSS (see Figure 80.). In addition, the WDT must be inactive and the POF flag must be set. 4. Capacitance loading on Ports 0 and 2 may cause spurious noise pulses to be superimposed on the VOLs of ALE and Ports 1 and 3. The noise is due to external bus capacitance discharging into the Port 0 and Port 2 pins when these pins make 1 to 0 transitions during bus operation. In the worst cases (capacitive loading 100pF), the noise pulse on the ALE line may exceed 0.45V with maxi VOL peak 0.6V. A Schmitt Trigger use is not necessary. 5. Typicals are based on a limited number of samples and are not guaranteed. The values listed are at room temperature. 6. Under steady state (non-transient) conditions, IOL must be externally limited as follows: Maximum IOL per port pin: 10 mA Maximum IOL per 8-bit port: Port 0: 26 mA Ports 1, 2, 3 and 4: 15 mA Maximum total IOL for all output pins: 71 mA If IOL exceeds the test condition, VOL may exceed the related specification. Pins are not guaranteed to sink current greater than the listed test conditions.
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Power Fail Detect at Ambiant Temperatures
VPFDP(1) 2.5V typ Note: VPFDM(2) 2.35V typ Hysterisis 100mV min.
1. Threshold Voltage for PFD Release 2. Threshold Voltage for PFD Activation
Figure 78. ICC Test Condition, Active Mode
VCC ICC VCC VCC RST (NC) CLOCK SIGNAL XTAL2 XTAL1 VSS All other pins are disconnected. P0 EA VCC
Figure 79. ICC Test Condition, Idle Mode
VCC ICC VCC P0 RST (NC) CLOCK SIGNAL XTAL2 XTAL1 VSS EA VCC
All other pins are disconnected.
Figure 80. ICC Test Condition, Power-Down Mode
VCC ICC VCC P0 RST (NC) XTAL2 XTAL1 VSS All other pins are disconnected. EA VCC
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Figure 81. Clock Signal Waveform for ICC Tests in Active and Idle Modes
VCC-0.5V 0.45V TCLCH TCHCL TCLCH = TCHCL = 5ns. 0.7VCC 0.2VCC-0.1
DC Parameters for A/D Converter
Table 117. DC Parameters for AD Converter in Precision Conversion
Symbol Parameter AVin Rref Vref(3) Cai Rai INL DNL OE Analog input voltage Resistance between Vref and Vss Reference voltage Analog input Capacitance Analog input Resistor Integral non linearity Differential non linearity Offset error -2 1 3 0.5 1 2 lsb lsb Min Vss- 0.2 12 2.40 60 400 2 lsb Automotive 16 Typ(1),(2) Max Unit V k V pF During sampling During sampling Test Conditions
Vref + 0.2
24 3.00
Note:
1. Typicals are based on a limited number of samples and are not guaranteed. 2. For temperatures higher than 85C, use standard conversion (8-bit only) and PRS > 2. 3. VREF < VCC + 0.2V for temperatures higher than 85.
AC Parameters
Explanation of the AC Symbols Each timing symbol has 5 characters. The first character is always a "T" (stands for time). The other characters, depending on their positions, stand for the name of a signal or the logical status of that signal. The following is a list of all the characters and what they stand for. Example: TAVLL = Time for Address Valid to ALE Low. TLLPL = Time for ALE Low to PSEN Low. TA = -40C to +85C; VSS = 0V; VCC = 3V to 5.5V; F = 0 to 40 MHz. (Load Capacitance for port 0, ALE and PSEN = 60 pF; Load Capacitance for all other outputs = 60 pF.) Table 118, Table 121 and Table 124 give the description of each AC symbols. Table 119, Table 123 and Table 125 give for each range the AC parameter. Table 120, Table 123 and Table 126 give the frequency derating formula of the AC parameter for each speed range description. To calculate each AC symbols: Take the x value and use this value in the formula. Example: TLLIV and 20 MHz, Standard clock. x = 30 ns T = 50 ns TCCIV = 4T - x = 170 ns
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External Program Memory Characteristics
Table 118. Symbol Description
Symbol T TLHLL TAVLL TLLAX TLLIV TLLPL TPLPH TPLIV TPXIX TPXIZ TAVIV TPLAZ Parameter Oscillator clock period ALE pulse width Address Valid to ALE Address Hold After ALE ALE to Valid Instruction In ALE to PSEN PSEN Pulse Width PSEN to Valid Instruction In Input Instruction Hold After PSEN Input Instruction Float After PSEN Address to Valid Instruction In PSEN Low to Address Float
Table 119. AC Parameters for a Fix Clock (F = 40 MHz)
Symbol T TLHLL TAVLL TLLAX TLLIV TLLPL TPLPH TPLIV TPXIX TPXIZ TAVIV TPLAZ 0 18 85 10 15 55 35 Min 25 40 10 10 70 Max Units ns ns ns ns ns ns ns ns ns ns ns ns
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Table 120. AC Parameters for a Variable Clock
Symbol TLHLL TAVLL TLLAX TLLIV TLLPL TPLPH TPLIV TPXIX TPXIZ TAVIV TPLAZ Type Min Min Min Max Min Min Max Min Max Max Max Standard Clock 2T-x T-x T-x 4T-x T-x 3T-x 3T-x x T-x 5T-x x X2 Clock T-x 0.5 T - x 0.5 T - x 2T-x 0.5 T - x 1.5 T - x 1.5 T - x x 0.5 T - x 2.5 T - x x X parameter 10 15 15 30 10 20 40 0 7 40 10 Units ns ns ns ns ns ns ns ns ns ns ns
External Program Memory Read Cycle
12 TCLCL TLHLL ALE TLLIV TLLPL TPLPH PSEN TLLAX TAVLL INSTR IN A0-A7 TAVIV PORT 2 ADDRESS OR SFR-P2 ADDRESS A8-A15 ADDRESS A8-A15 TPLIV TPLAZ TPXAV TPXIZ A0-A7 INSTR IN
TPXIX INSTR IN
PORT 0
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External Data Memory Characteristics
Table 121. Symbol Description
Symbol TRLRH TWLWH TRLDV TRHDX TRHDZ TLLDV TAVDV TLLWL TAVWL TQVWX TQVWH TWHQX TRLAZ TWHLH Parameter RD Pulse Width WR Pulse Width RD to Valid Data In Data Hold After RD Data Float After RD ALE to Valid Data In Address to Valid Data In ALE to WR or RD Address to WR or RD Data Valid to WR Transition Data set-up to WR High Data Hold After WR RD Low to Address Float RD or WR High to ALE high
Table 122. AC Parameters for a Fix Clock (F=40MHz)
Symbol TRLRH TWLWH TRLDV TRHDX TRHDZ TLLDV TAVDV TLLWL TAVWL TQVWX TQVWH TWHQX TRLAZ TWHLH 10 50 75 10 160 15 0 40 0 30 160 165 100 Min 130 130 100 Max Units ns ns ns ns ns ns ns ns ns ns ns ns ns ns
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Table 123. AC Parameters for a Variable Clock
Symbol TRLRH TWLWH TRLDV TRHDX TRHDZ TLLDV TAVDV TLLWL TLLWL TAVWL TQVWX TQVWH TWHQX TRLAZ TWHLH TWHLH Type Min Min Max Min Max Max Max Min Max Min Min Min Min Max Min Max Standard Clock 6T-x 6T-x 5T-x x 2T-x 8T-x 9T-x 3T-x 3T+x 4T-x T-x 7T-x T-x x T-x T+x X2 Clock 3T-x 3T-x 2.5 T - x x T-x 4T -x 4.5 T - x 1.5 T - x 1.5 T + x 2T-x 0.5 T - x 3.5 T - x 0.5 T - x x 0.5 T - x 0.5 T + x X parameter 20 20 25 0 20 40 60 25 25 25 15 25 10 0 15 15 Units ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
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External Data Memory Write Cycle
ALE TWHLH
PSEN
TLLWL
TWLWH
WR TLLAX PORT 0 A0-A7 ADDRESS OR SFR-P2 TAVWL ADDRESS A8-A15 OR SFR P2 TQVWX TQVWH DATA OUT TWHQX
PORT 2
External Data Memory Read Cycle
ALE TLLDV TWHLH
PSEN
TLLWL
TRLRH TRHDZ TRHDX DATA IN TRLAZ ADDRESS A8-A15 OR SFR P2
RD TLLAX PORT 0 ADDRESS OR SFR-P2 A0-A7 TAVWL
TAVDV
PORT 2
Serial Port Timing - Shift Register Mode Table 124. Symbol Description (F = 40 MHz)
Symbol TXLXL TQVHX TXHQX TXHDX TXHDV Parameter Serial port clock cycle time Output data set-up to clock rising edge Output data hold after clock rising edge Input data hold after clock rising edge Clock rising edge to input data valid
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Table 125. AC Parameters for a Fix Clock (F = 40 MHz)
Symbol TXLXL TQVHX TXHQX TXHDX TXHDV Min 300 200 30 0 117 Max Units ns ns ns ns ns
Table 126. AC Parameters for a Variable Clock
Symbol TXLXL TQVHX TXHQX TXHDX TXHDV Type Min Min Min Min Max Standard Clock 12 T 10 T - x 2T-x x 10 T - x X2 Clock 6T 5T-x T-x x 5 T- x 50 20 0 133 X parameter for -M range Units ns ns ns ns ns
Shift Register Timing Waveforms
INSTRUCTION ALE TXLXL CLOCK TQVXH OUTPUT DATA WRITE to SBUF INPUT DATA CLEAR RI TXHQX 0 TXHDV
VALID VALID
0
1
2
3
4
5
6
7
8
1
2 TXHDX
VALID
3
4
5
6
7 SET TI
VALID
VALID
VALID
VALID
VALID
SET RI
External Clock Drive Characteristics (XTAL1)
Table 127. AC Parameters
Symbol TCLCL TCHCX TCLCX TCLCH TCHCL TCHCX/TCLCX Parameter Oscillator Period High Time Low Time Rise Time Fall Time Cyclic ratio in X2 mode 40 Min 25 5 5 5 5 60 Max Units ns ns ns ns ns %
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External Clock Drive Waveforms
VCC-0.5V 0.45V
0.7VCC 0.2VCC-0.1 TCHCL TCLCX TCLCL TCHCX TCLCH
AC Testing Input/Output Waveforms
INPUT/OUTPUT
VCC -0.5V 0.45V
0.2 VCC + 0.9 0.2 VCC - 0.1
AC inputs during testing are driven at VCC - 0.5 for a logic "1" and 0.45V for a logic "0". Timing measurement are made at VIH min for a logic "1" and VIL max for a logic "0". Float Waveforms
FLOAT VOH - 0.1 V VOL + 0.1 V VLOAD VLOAD + 0.1 V VLOAD - 0.1 V
For timing purposes as port pin is no longer floating when a 100 mV change from load voltage occurs and begins to float when a 100 mV change from the loaded VOH/VOL level occurs. IOL/IOH 20 mA.
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Clock Waveforms
STATE4 P1 P2
Valid in normal clock mode. In X2 mode XTAL2 must be changed to XTAL2/2.
STATE5 P1 P2 STATE6 P1 P2 STATE1 P1 P2 STATE2 P1 P2 STATE3 P1 P2 STATE4 P1 P2 STATE5 P1 P2
INTERNAL
CLOCK XTAL2 ALE
EXTERNAL PROGRAM MEMORY FETCH PSEN P0 DATA SAMPLED FLOAT PCL OUT DATA SAMPLED FLOAT
THESE SIGNALS ARE NOT ACTIVATED DURING THE EXECUTION OF A MOVX INSTRUCTION
PCL OUT
DATA SAMPLED FLOAT
PCL OUT
P2 (EXT) READ CYCLE RD
INDICATES ADDRESS TRANSITIONS
PCL OUT (IF PROGRAM MEMORY IS EXTERNAL)
P0
P2 WRITE CYCLE
DPL OR Rt OUT
DATA SAMPLED FLOAT
INDICATES DPH OR P2 SFR TO PCH TRANSITION
WR P0
P2 PORT OPERATION MOV PORT SRC MOV DEST P0 OLD DATA NEW DATA P0 PINS SAMPLED P1, P2, P3 PINS SAMPLED DPL OR Rt OUT DATA OUT
PCL OUT (EVEN IF PROGRAM MEMORY IS INTERNAL)
PCL OUT (IF PROGRAM MEMORY IS EXTERNAL
INDICATES DPH OR P2 SFR TO PCH TRANSITION
P0 PINS SAMPLED P1, P2, P3 PINS SAMPLED
MOV DEST PORT (P1. P2. P3) (INCLUDES INTO. INT1. TO T1) SERIAL PORT SHIFT CLOCK TXD (MODE 0)
RXD SAMPLED
RXD SAMPLED
This diagram indicates when signals are clocked internally. The time it takes the signals to propagate to the pins, however, ranges from 25 to 125 ns. This propagation delay is dependent on variables such as temperature and pin loading. Propagation also varies from output to output and component. Typically though (TA=25C fully loaded) RD and WR propagation delays are approximately 50ns. The other signals are typically 85 ns. Propagation delays are incorporated in the AC specifications.
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Flash/EEPROM Memory
Table 128. Timing Symbol Definitions
Signals S (Hardware condition) R B PSEN#,EA RST FBUSY flag L V X Conditions Low Valid No Longer Valid
Table 129. Memory AC Timing VDD = 3V to 5.5V, TA = -40 to +85C
Symbol TSVRL TRLSX TBHBL Parameter Input PSEN# Valid to RST Edge Input PSEN# Hold after RST Edge Flash/EEPROM Internal Busy (Programming) Time Min 50 50 10 Typ Max Unit ns ns ms
Figure 82. Flash Memory - ISP Waveforms
RST TSVRL PSEN#1 TRLSX
Figure 83. Flash Memory - Internal Busy Waveforms
FBUSY bit TBHBL
A/D Converter
Table 130. AC Parameters for A/D Conversion
Symbol TSETUP ADC Clock Frequency Parameter Min 4 700 Typ Max Unit s KHz
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Timings
Test conditions: capacitive load on all pins= 60 pF.
Table 1. SPI Interface Master AC Timing VDD = 2.7 to 3.3 V, TA = -40 to +85C
Symbol Parameter Slave Mode TCHCH TCHCX TCLCX TSLCH, TSLCL TIVCL, TIVCH TCLIX, TCHIX TCLOV, TCHOV TCLOX, TCHOX TCLSH, TCHSH TSLOV TSHOX TSHSL TOLOH TOHOL Clock Period Clock High Time Clock Low Time SS Low to Clock edge Input Data Valid to Clock Edge Input Data Hold after Clock Edge Output Data Valid after Clock Edge Output Data Hold Time after Clock Edge SS High after Clock Edge SS Low to Output Data Valid 0 4TPER+20ns(1) 4TPER+20ns
(1)
Min
Max
Unit
6(1) 3
(1)
TPER TPER TPER
(1)
3(1) 4TPER-20ns 50 50 50
ns ns ns ns ns ns ns
Output Data Hold after SS High 2TPER+120ns(1)
2TPER+100ns(1)
ns
SS High to SS Low Output Rise time Output Fall Time Master Mode
100 100
ns ns
TCHCH TCHCX TCLCX TIVCL, TIVCH TCLIX, TCHIX TCLOV, TCHOV TCLOX, TCHOX TCLCH TCHCL
Clock Period Clock High Time Clock Low Time Input Data Valid to Clock Edge Input Data Hold after Clock Edge Output Data Valid after Clock Edge Output Data Hold Time after Clock Edge Output Data Rise time Output Data Fall Time
4(1) 2TPER-20ns(1) 2TPER-20ns(1) 50 0 20 0 100 100
TPER TPER TPER ns ns ns ns ns ns
Note:
1. Value of this parameter depends on prescacler ratio defined in bits 0,1 and 7 of SCON Register.In the above table, the ratio used is 4. As it can be set also to 8, 16, 32, 64 or 128, the factor of TPER must be changed according to the new ratio.E.g. 2TPER-20ns(1) will be changed to 4TPER-20ns(1) if the prescaler ratio equals 8.
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Waveforms
Figure 84. SPI Slave Waveforms (SSCPHA= 0)
SS (input) TSLCH TSLCL SCK (SSCPOL= 0) (input) SCK (SSCPOL= 1) (input) TSLOV MISO (output) SLAVE MSB OUT TIVCH TCHIX TIVCL TCLIX MOSI (input) MSB IN BIT 6 LSB IN TCHCH TCLCH
TCLSH TCHSH
TSHSL
TCHCX
TCLCX
TCHCL
TCLOV TCHOV BIT 6
TCLOX TCHOX SLAVE LSB OUT
(1)
TSHOX
Note:
1. Not Defined but generally the MSB of the character which has just been received.
Figure 85. SPI Slave Waveforms (SSCPHA= 1)
SS (input) TSLCH TSLCL SCK (SSCPOL= 0) (input) SCK (SSCPOL= 1) (input) TSLOV MISO (output)
(1)
TCHCH
TCLCH
TCLSH TCHSH
TSHSL
TCHCX
TCLCX
TCHCL TCHOV TCLOV BIT 6
TCHOX TCLOX SLAVE LSB OUT
TSHOX
SLAVE MSB OUT TIVCH TCHIX TIVCL TCLIX
MOSI (input)
MSB IN
BIT 6
LSB IN
Note:
1. Not Defined but generally the LSB of the character which has just been received.
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Figure 86. SPI Master Waveforms (SSCPHA= 0)
SS (output) TCHCH SCK (SSCPOL= 0) (output) SCK (SSCPOL= 1) (output) TCLCH
TCHCX
TCLCX
TCHCL
TIVCH TCHIX TIVCL TCLIX MSB IN BIT 6 TCLOV TCHOV Port Data MSB OUT BIT 6 LSB OUT LSB IN TCLOX TCHOX Port Data
MOSI (input)
MISO (output)
Note:
1. SS handled by software using general purpose port pin.
Figure 87. SPI Master Waveforms (SSCPHA= 1)
SS(1) (output) TCHCH SCK (SSCPOL= 0) (output) SCK (SSCPOL= 1) (output) TCLCH
TCHCX
TCLCX
TCHCL
TIVCH TCHIX TIVCL TCLIX
MOSI (input)
MSB IN TCLOV TCHOV Port Data MSB OUT
BIT 6 TCLOX TCHOX BIT 6
LSB IN
MISO (output)
LSB OUT
Port Data
Note: Note:
1. SS handled by software using general purpose port pin.
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Ordering Information
Table 131. Possible Order Entries
Part Number AT89C51CC03U-7CTIM AT89C51CC03U-RLTIM AT89C51CC03U-SLSIM AT89C51CC03C-7CTIM AT89C51CC03C-RLTIM AT89C51CC03C-SLSIM AT89C51CC03U-RDTIM AT89C51CC03U-S3SIM AT89C51CC03C-RDTIM AT89C51CC03C-S3SIM Boot Loader UART UART UART CAN CAN CAN UART UART CAN CAN Temperature Range -40 to +85C -40 to +85C -40 to +85C -40 to +85C -40 to +85C -40 to +85C -40 to +85C -40 to +85C -40 to +85C -40 to +85C Quality Grade(1) Industrial Industrial Industrial Industrial Industrial Industrial Industrial Industrial Industrial Industrial Package CA-BGA64 VQFP44 PLCC44 CA-BGA64 VQFP44 PLCC44 VQFP64 PLCC52 VQFP64 PLCC52 Packing Tray Tray Stick Tray Tray Stick Tray Stick Tray Stick Product Marking 89C51CC03UA-IM 89C51CC03UA-IM 89C51CC03UA-IM 89C51CC03CA-IM 89C51CC03CA-IM 89C51CC03CA-IM 89C51CC03UA-IM 89C51CC03UA-IM 89C51CC03CA-IM 89C51CC03CA-IM
AT89C51CC03UA-7CTUM AT89C51CC03UA-RLTUM AT89C51CC03UA-SLSUM AT89C51CC03CA-7CTUM AT89C51CC03CA-RLTUM AT89C51CC03CA-SLSUM AT89C51CC03UA-RDTUM AT89C51CC03UA-S3SUM
UART UART UART CAN CAN CAN UART UART
-40 to +85C -40 to +85C -40 to +85C -40 to +85C -40 to +85C -40 to +85C -40 to +85C -40 to +85C
Industrial & Green Industrial & Green Industrial & Green Industrial & Green Industrial & Green Industrial & Green Industrial & Green Industrial & Green
CA-BGA64 VQFP44 PLCC44 CA-BGA64 VQFP44 PLCC44 VQFP64 PLCC52
Tray Tray Stick Tray Tray Stick Tray Stick
89C51CC03UA-UM 89C51CC03UA-UM 89C51CC03UA-UM 89C51CC03CA-UM 89C51CC03CA-UM 89C51CC03CA-UM 89C51CC03UA-UM 89C51CC03UA-UM
AT89C51CC03UA-RLTZM AT89C51CC03CA-RLTZM AT89C51CC03UA-RDTZM AT89C51CC03CA-RDTZM
UART CAN UART CAN
-40 to +125C -40 to +125C -40 to +125C -40 to +125C
Automotive & Green Automotive & Green Automotive & Green Automotive & Green
VQFP44 VQFP44 VQFP64 VQFP64
Tray Tray Tray Tray
89C51CC03UA-ZM 89C51CC03CA-ZM 89C51CC03UA-ZM 89C51CC03CA-ZM
Note:
1. Automotive grade indicates production flow according to ISO-TS-16949 and automotive product qualification as per AECQ100.
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Package Drawing
CA-BGA
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VQFP44
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PLCC44
187
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VQFP64
188
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PLCC52
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Datasheet Change Log
Changes from 4182B 09/03 to 4182C 12/03 Changes from 4182C 12/03 to 4182D 01/04
1. Added Icc Idle, IPD, and Rrst value in "DC Parameters for A/D Converter" on page 171. 1. Updated SFR Table. - - - - SFR : SPSTR changed to SPSCR CANSTMH changed to CANSTMPH p15 CANSTML changed to CANSTMPL p15 CANCONC changed to CANCONCH p15
2. AC/DC - p.160 IccOP and ICCIdle formulas changed 3. Changed maximum frequency to 60MHz in internal code execution.
Changes from 4182D 01/04 to 4182E 05/04 Changes from 4182E 05/04 to 4182F 10/04 Changes from 4182F 10/04 to 4182G 03/05 Changes from 4182G 03/05 to 4182H 04/05 Changes from 4182H 04/05 to 4182I 06/05
1. Added Automotive temperature range.
1. Various minor corrections throughout the document.
1. Change to Watchdog formula, Section "Watchdog Programming", page 83.
1. Refined automotive temperature values.
1. Added Green product ordering information. 2. Clarification in Waveform diagram, page 20.
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Table of Contents
Features ................................................................................................. 1 Description ............................................................................................ 2 Block Diagram ...................................................................................... 2 Pin Configuration ................................................................................. 3
CA-BGA64 Top View ............................................................................................ 5 I/O Configurations................................................................................................. 8 Port 1, Port 3 and Port 4 ....................................................................................... 8 Port 0 and Port 2................................................................................................... 9 Read-Modify-Write Instructions .......................................................................... 10 Quasi-Bidirectional Port Operation ..................................................................... 11
SFR Mapping ....................................................................................... 12 Clock .................................................................................................... 18
Description.......................................................................................................... 18 Registers............................................................................................................. 21
Data Memory ....................................................................................... 23
Internal Space..................................................................................................... External Space ................................................................................................... Dual Data Pointer ............................................................................................... Registers............................................................................................................. 24 25 27 28
Power Monitor ..................................................................................... 30
Description.......................................................................................................... 30
Reset .................................................................................................... 32
Introduction ......................................................................................................... 32 Reset Input ......................................................................................................... 32 Reset Output ....................................................................................................... 33
Power Management ............................................................................ 34
Introduction ......................................................................................................... Idle Mode ............................................................................................................ Power-Down Mode ............................................................................................. Registers............................................................................................................. 34 34 34 37
EEPROM Data Memory ...................................................................... 38
Write Data in the Column Latches ...................................................................... 38 Programming ...................................................................................................... 38 Read Data........................................................................................................... 38 i
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Examples ............................................................................................................ 39 Registers............................................................................................................. 40
Program/Code Memory ...................................................................... 41
External Code Memory Access .......................................................................... 42 Flash Memory Architecture................................................................................. 43 Overview of FM0 Operations .............................................................................. 47
Operation Cross Memory Access ..................................................... 56 Sharing Instructions ........................................................................... 57 In-System Programming (ISP) ........................................................... 59
Flash Programming and Erasure........................................................................ Boot Process ...................................................................................................... Application Programming Interface..................................................................... XROW Bytes....................................................................................................... Hardware Security Byte ...................................................................................... 59 59 61 61 62
Serial I/O Port ..................................................................................... 63
Framing Error Detection .................................................................................... Automatic Address Recognition.......................................................................... Given Address ................................................................................................... Broadcast Address ............................................................................................ Registers............................................................................................................. 63 64 65 65 66
Timers/Counters ................................................................................. 69
Timer/Counter Operations .................................................................................. Timer 0................................................................................................................ Timer 1................................................................................................................ Interrupt .............................................................................................................. Registers............................................................................................................. 69 69 72 73 73
Timer 2 ................................................................................................. 77
Auto-Reload Mode............................................................................................. 77 Programmable Clock-Output .............................................................................. 78 Registers............................................................................................................. 79
Watchdog Timer ................................................................................. 82
Watchdog Programming ..................................................................................... 83 Watchdog Timer During Power-down Mode and Idle ......................................... 84
CAN Controller .................................................................................... 86
CAN Protocol ...................................................................................................... 86 CAN Controller Description................................................................................. 90 CAN Controller Mailbox and Registers Organization.......................................... 91
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CAN Controller Management.............................................................................. 93 IT CAN Management .......................................................................................... 95 Bit Timing and Baud Rate ................................................................................... 97 Fault Confinement .............................................................................................. 99 Acceptance Filter .............................................................................................. 100 Data and Remote Frame .................................................................................. 101 Time Trigger Communication (TTC) and Message Stamping .......................... 102 CAN Autobaud and Listening Mode ................................................................. 103 Routines Examples........................................................................................... 103 CAN SFR's ....................................................................................................... 106 Registers........................................................................................................... 107
Serial Port Interface (SPI) ................................................................ 130
Features............................................................................................................ 130 Signal Description............................................................................................. 130 Functional Description ...................................................................................... 132
Programmable Counter Array (PCA) .............................................. 141
PCA Timer ........................................................................................................ PCA Modules.................................................................................................... PCA Interrupt .................................................................................................... PCA Capture Mode........................................................................................... 16-bit Software Timer Mode ............................................................................. High Speed Output Mode ................................................................................. Pulse Width Modulator Mode............................................................................ PCA WatchDog Timer ...................................................................................... PCA Registers .................................................................................................. 141 142 143 143 144 145 145 146 147
Analog-to-Digital Converter (ADC) ................................................. 152
Features............................................................................................................ ADC Port1 I/O Functions .................................................................................. ADC Converter Operation................................................................................. Voltage Conversion .......................................................................................... Clock Selection ................................................................................................. ADC Standby Mode .......................................................................................... IT ADC Management ........................................................................................ Routines examples ........................................................................................... Registers........................................................................................................... 152 152 154 154 154 155 155 155 157
Interrupt System ............................................................................... 160
Introduction ....................................................................................................... 160 Registers........................................................................................................... 162
Electrical Characteristics ................................................................. 168
Absolute Maximum Ratings .............................................................................168 ICCOP Test Conditions .................................................................................... 168
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DC Parameters for Standard Voltage ...............................................................168 DC Parameters for A/D Converter .................................................................... 171 AC Parameters .................................................................................................171 Timings ............................................................................................................. 181
Ordering Information ........................................................................ 184
.......................................................................................................................... 184
Package Drawing .............................................................................. 185
CA-BGA ............................................................................................................ VQFP44 ............................................................................................................ PLCC44 ............................................................................................................ VQFP64 ............................................................................................................ PLCC52 ............................................................................................................ 185 186 187 188 189
Datasheet Change Log ..................................................................... 190
Changes from 4182B - 09/03 to 4182C 12/03 .................................................. Changes from 4182C - 12/03 to 4182D 01/04.................................................. Changes from 4182D - 01/04 to 4182E 05/04 .................................................. Changes from 4182E -05/04 to 4182F 10/04 ................................................... Changes from 4182F - 10/04 to 4182G 03/05 .................................................. Changes from 4182G 03/05 to 4182H 04/05.................................................... Changes from 4182H 04/05 to 4182I 06/05...................................................... 190 190 190 190 190 190 190
Table of Contents .................................................................................. i
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